| /drivers/gpio/ |
| A D | gpio-mb86s7x.c | 30 #define DDR(x) (0x10 + x / 8 * 4) macro
81 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
83 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
106 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
108 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
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| /drivers/perf/amlogic/ |
| A D | Kconfig | 3 tristate "Amlogic DDR Bandwidth Performance Monitor"
6 Provides support for the DDR performance monitor
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| /drivers/perf/ |
| A D | Kconfig | 166 tristate "Freescale i.MX8 DDR perf monitor"
169 Provides support for the DDR performance monitor in i.MX8, which
174 tristate "Freescale i.MX9 DDR perf monitor"
177 Provides support for the DDR performance monitor in i.MX9, which
259 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
262 Support for Driveway PMU events monitoring on Yitian 710 DDR
271 Enable perf support for Marvell DDR Performance monitoring
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| /drivers/mtd/lpddr/ |
| A D | Kconfig | 10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
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| /drivers/memory/ |
| A D | Kconfig | 11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
52 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
93 select DDR
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| /drivers/memory/tegra/ |
| A D | Kconfig | 19 select DDR
31 select DDR
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| /drivers/edac/ |
| A D | Kconfig | 322 tristate "Freescale Layerscape DDR"
477 bool "Marvell Armada XP DDR and L2 Cache ECC"
481 DDR RAM and L2 cache controllers.
484 tristate "Synopsys DDR Memory Controller"
487 Support for error detection and correction on the Synopsys DDR
549 tristate "Nuvoton NPCM DDR Memory Controller"
552 Support for error detection and correction on the Nuvoton NPCM DDR
560 tristate "Xilinx Versal DDR Memory Controller"
563 Support for error detection and correction on the Xilinx Versal DDR
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| /drivers/clk/sophgo/ |
| A D | Kconfig | 20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
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| /drivers/clk/baikal-t1/ |
| A D | Kconfig | 27 CPUs, DDR, etc.) or passed over the clock dividers to be only
50 can be directly asserted/de-asserted (PCIe and DDR sub-domains).
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| /drivers/pinctrl/tegra/ |
| A D | pinctrl-tegra30.c | 2200 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, …
2201 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, …
2202 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, …
2259 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, …
2260 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, …
2261 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, …
2262 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, …
2263 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, …
2264 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, …
2265 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, …
[all …]
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| /drivers/accel/qaic/ |
| A D | qaic_ras.c | 49 DDR, enumerator
59 [DDR] = "DDR",
236 case DDR: in ras_msg_to_cpu()
383 case DDR: in decode_ras_msg()
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| /drivers/perf/hisilicon/ |
| A D | Kconfig | 7 Agent performance monitor and DDR Controller performance monitor.
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| /drivers/memory/samsung/ |
| A D | Kconfig | 13 select DDR
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| /drivers/devfreq/event/ |
| A D | Kconfig | 40 (DDR Monitor Module) driver to count ddr load.
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| /drivers/dma/qcom/ |
| A D | Kconfig | 32 transfer data between DDR and peripheral.
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| /drivers/clk/at91/ |
| A D | sama7g5.c | 387 .ep = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), },
395 .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0),
582 .pp = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), },
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| A D | sama7d65.c | 474 .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), },
482 .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), },
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| /drivers/devfreq/ |
| A D | Kconfig | 118 This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
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| /drivers/mmc/host/ |
| A D | omap_hsmmc.c | 97 #define DDR (1 << 19) macro
591 con |= DDR; /* configure in DDR mode */ in omap_hsmmc_set_bus_width()
593 con &= ~DDR; in omap_hsmmc_set_bus_width()
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| /drivers/iio/dac/ |
| A D | Kconfig | 30 QSPI + DDR (Double Data Rate) bus.
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| /drivers/hid/ |
| A D | Kconfig | 1175 Note that DDR (Dance Dance Revolution) mode is not supported, nor
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| /drivers/regulator/ |
| A D | Kconfig | 1435 peripherals such as DDR, Flash memories and system devices.
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| /drivers/hwmon/ |
| A D | Kconfig | 2298 this will typically be done from DMI DDR detection code in the
|