Home
last modified time | relevance | path

Searched refs:DF (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
51 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v1_7_enable_broadcast_mode()
53 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
88 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
91 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
93 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
96 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
109 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
117 WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0, in df_v1_7_enable_ecc_force_par_wr_rmw()
A Ddf_v3_6.c227 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl); in df_v3_6_query_hashes()
268 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v3_6_enable_broadcast_mode()
270 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v3_6_enable_broadcast_mode()
272 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v3_6_enable_broadcast_mode()
314 tmp = RREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
318 WREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
321 tmp = RREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
325 WREG32_SOC15(DF, 0, in df_v3_6_update_medium_grain_clock_gating()
340 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v3_6_get_clockgating_state()
645 hw_assert_msklo = RREG32_SOC15(DF, 0, in df_v3_6_query_ras_poison_mode()
[all …]
A Ddf_v4_15.c37 tmp = RREG32_SOC15(DF, 0, regNCSConfigurationRegister1); in df_v4_15_hw_init()
39 WREG32_SOC15(DF, 0, regNCSConfigurationRegister1, tmp); in df_v4_15_hw_init()
A Ddf_v4_3.c34 hw_assert_msklo = RREG32_SOC15(DF, 0, in df_v4_3_query_ras_poison_mode()
36 hw_assert_mskhi = RREG32_SOC15(DF, 0, in df_v4_3_query_ras_poison_mode()
/drivers/scsi/
A Daha1542.c133 if (!wait_mask(STATUS(base), DF, DF, 0, timeout)) in aha1542_in()
225 if (!wait_mask(STATUS(sh->io_port), STATMASK, INIT | IDLE, STST | DIAGF | INVDCMD | DF | CDF, 0)) in aha1542_test_port()
240 if (!wait_mask(STATUS(sh->io_port), DF, DF, 0, 0)) in aha1542_test_port()
246 if (inb(STATUS(sh->io_port)) & DF) in aha1542_test_port()
550 if (i & DF) { in aha1542_getconfig()
655 if (i & DF) { in aha1542_query()
940 STATMASK, IDLE, STST | DIAGF | INVDCMD | DF | CDF, 0)) { in aha1542_reset()
A Daha1542.h15 #define DF BIT(2) /* Data In Port Full */ macro
18 #define STATMASK (STST | DIAGF | INIT | IDLE | CDF | DF | INVDCMD)
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega10_hwmgr.c943 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()

Completed in 862 milliseconds