| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.c | 319 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc32_stream_encoder_dp_unblank()
321 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); in enc32_stream_encoder_dp_unblank()
323 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); in enc32_stream_encoder_dp_unblank()
325 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0); in enc32_stream_encoder_dp_unblank()
327 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
329 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc32_stream_encoder_dp_unblank()
391 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); in enc32_set_dig_input_mode()
400 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc32_reset_fifo()
404 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc32_reset_fifo()
413 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc32_enable_fifo()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.c | 240 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1); in enc401_set_dig_input_mode()
243 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2); in enc401_set_dig_input_mode()
246 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3); in enc401_set_dig_input_mode()
249 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0); in enc401_set_dig_input_mode()
346 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc401_stream_encoder_dp_unblank()
348 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); in enc401_stream_encoder_dp_unblank()
350 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); in enc401_stream_encoder_dp_unblank()
352 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0); in enc401_stream_encoder_dp_unblank()
354 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); in enc401_stream_encoder_dp_unblank()
356 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc401_stream_encoder_dp_unblank()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.c | 58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc314_reset_fifo()
62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc314_reset_fifo()
71 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc314_enable_fifo()
76 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc314_enable_fifo()
83 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); in enc314_disable_fifo()
91 REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val); in enc314_is_fifo_enabled()
428 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); in enc314_set_dig_input_mode()
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| A D | dcn314_dio_stream_encoder.h | 110 SRI(DIG_FIFO_CTRL0, DIG, id)
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.c | 385 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc35_reset_fifo()
389 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc35_reset_fifo()
399 REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val); in enc35_is_fifo_enabled()
406 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); in enc35_disable_fifo()
415 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc35_enable_fifo()
422 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc35_enable_fifo()
430 REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, &value); in enc35_get_pixels_per_cycle()
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| A D | dcn35_dio_stream_encoder.h | 110 SRI(DIG_FIFO_CTRL0, DIG, id),\
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 143 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.h | 189 uint32_t DIG_FIFO_CTRL0; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 222 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 308 SRI_ARR(DIG_FIFO_CTRL0, DIG, id)
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