| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_i2c_hw.h | 100 SR(DIO_MEM_PWR_CTRL),\
245 I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
269 uint32_t DIO_MEM_PWR_CTRL; member
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| A D | dce_i2c_hw.c | 328 if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) { in setup_engine()
329 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0); in setup_engine()
437 if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) in release_engine()
438 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); in release_engine()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.h | 26 SR(DIO_MEM_PWR_CTRL), \
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| A D | dcn36_resource.c | 583 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| A D | dcn31_hwseq.c | 240 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn31_init_hw()
244 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); in dcn31_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| A D | dce_hwseq.h | 197 SR(DIO_MEM_PWR_CTRL), \
422 SR(DIO_MEM_PWR_CTRL), \
634 uint32_t DIO_MEM_PWR_CTRL; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 165 SR(DIO_MEM_PWR_CTRL), \
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| A D | dcn35_resource.c | 602 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 362 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn201_init_hw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 675 SR(DIO_MEM_PWR_CTRL), \
765 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 266 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn35_init_hw()
270 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0); in dcn35_init_hw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 688 SR(DIO_MEM_PWR_CTRL), \
783 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 681 SR(DIO_MEM_PWR_CTRL), \
771 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 680 SR(DIO_MEM_PWR_CTRL), \
770 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 795 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn30_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 952 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn32_init_hw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 529 SR(DIO_MEM_PWR_CTRL), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 582 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 1276 I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR_I2C(DIO_MEM_PWR_CTRL, id), \
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| A D | dcn32_resource.c | 533 SR(DIO_MEM_PWR_CTRL), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 508 SR(DIO_MEM_PWR_CTRL), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 316 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn401_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 1849 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn10_init_hw()
|