Searched refs:DISPCLK (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 44 double DISPCLK; member
281 double DISPCLK,
919 myPipe->DISPCLK, in CalculatePrefetchSchedule()
969 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) in CalculatePrefetchSchedule()
1992 v->DISPCLK = v->DISPCLK_calculated; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2359 v->HTotal[k]) / v->DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2374 v->HTotal[k]) / v->DISPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2421 myPipe.DISPCLK = v->DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3277 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK); in CalculateDynamicMetadataParameters()
3282 *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; in CalculateDynamicMetadataParameters()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20v2.c | 65 double DISPCLK,
94 double DISPCLK,
472 double DISPCLK, in CalculateDelayAfterScaler() argument
520 if (DPPCLK == 0.0 || DISPCLK == 0.0) in CalculateDelayAfterScaler()
523 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK in CalculateDelayAfterScaler()
544 double DISPCLK, in CalculatePrefetchSchedule() argument
610 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); in CalculatePrefetchSchedule()
627 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; in CalculatePrefetchSchedule()
2026 / mode_lib->vba.DISPCLK; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2045 / mode_lib->vba.DISPCLK); in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| A D | display_mode_vba_20.c | 59 double DISPCLK,
442 double DISPCLK, in CalculatePrefetchSchedule() argument
528 if (DPPCLK == 0.0 || DISPCLK == 0.0) in CalculatePrefetchSchedule()
531 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK in CalculatePrefetchSchedule()
547 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); in CalculatePrefetchSchedule()
564 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; in CalculatePrefetchSchedule()
1990 / mode_lib->vba.DISPCLK; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2009 / mode_lib->vba.DISPCLK); in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2091 mode_lib->vba.DISPCLK, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5094 mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; in dml20_ModeSupportAndSystemConfigurationFull()
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| A D | dcn20_fpu.c | 1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 64 double DISPCLK; member
275 double DISPCLK,
928 myPipe->DISPCLK,
991 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
2129 v->DISPCLK = v->DISPCLK_calculated;
2513 v->HTotal[k]) / v->DISPCLK;
2529 v->HTotal[k]) / v->DISPCLK);
2596 myPipe.DISPCLK = v->DISPCLK;
3405 double DISPCLK, argument
3429 *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 62 double DISPCLK; member
284 double DISPCLK,
946 myPipe->DISPCLK,
1009 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
2147 v->DISPCLK = v->DISPCLK_calculated;
2532 v->HTotal[k]) / v->DISPCLK;
2548 v->HTotal[k]) / v->DISPCLK);
2615 myPipe.DISPCLK = v->DISPCLK;
3511 double DISPCLK, argument
3535 *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 43 double DISPCLK; member
737 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) in CalculatePrefetchSchedule()
741 + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay; in CalculatePrefetchSchedule()
756 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK); in CalculatePrefetchSchedule()
773 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / myPipe->DISPCLK; in CalculatePrefetchSchedule()
2052 / mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2071 / mode_lib->vba.DISPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2138 myPipe.DISPCLK = mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3432 myPipe.DISPCLK = locals->RequiredDISPCLK[i][j]; in CalculatePrefetchSchedulePerPlane()
5217 mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; in dml21_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.c | 1096 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz; in ModeSupportAndSystemConfiguration()
1098 mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz; in ModeSupportAndSystemConfiguration()
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| A D | display_mode_vba.h | 436 double DISPCLK; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_32.c | 611 mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
628 mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
764 …pSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dispclk = mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3737 …mode_lib->vba.DISPCLK = mode_lib->vba.RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombin… in dml32_ModeSupportAndSystemConfigurationFull()
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| A D | dcn32_fpu.c | 1659 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn32_calculate_dlg_params()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | sienna_cichlid_ppt.c | 176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
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| A D | navi10_ppt.c | 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core.c | 355 dml_float_t DISPCLK,
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