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Searched refs:DISPC_CONTROL (Results 1 – 4 of 4) sorted by relevance

/drivers/video/fbdev/omap2/omapfb/dss/
A Ddispc.c174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
2804 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2812 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
2926 l = dispc_read_reg(DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
2929 dispc_write_reg(DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
[all …]
A Ddispc.h18 #define DISPC_CONTROL 0x0040 macro
/drivers/gpu/drm/omapdrm/dss/
A Ddispc.c262 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
263 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
264 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
265 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
266 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
285 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
287 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
2935 l = dispc_read_reg(dispc, DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
2938 dispc_write_reg(dispc, DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
3130 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
[all …]
A Ddispc.h16 #define DISPC_CONTROL 0x0040 macro

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