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Searched refs:DISPC_IRQENABLE (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/omapdrm/dss/
A Ddispc.h15 #define DISPC_IRQENABLE 0x001C macro
A Ddispc.c3360 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3628 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3633 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); in dispc_write_irqenable()
3636 dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
/drivers/video/fbdev/omap2/omapfb/dss/
A Ddispc.h17 #define DISPC_IRQENABLE 0x001C macro
A Ddispc.c3396 DUMPREG(DISPC_IRQENABLE); in dispc_dump_regs()
3661 return dispc_read_reg(DISPC_IRQENABLE); in dispc_read_irqenable()
3667 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); in dispc_write_irqenable()
3672 dispc_write_reg(DISPC_IRQENABLE, mask); in dispc_write_irqenable()

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