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Searched refs:DISPLAY_INFO (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_display_device.h148 #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
149 #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
155 #define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi)
164 #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst)
165 #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb)
175 #define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch)
177 #define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
179 #define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc)
185 #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay)
187 #define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr)
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A Dintel_display_reg_defs.h11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
42 #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
43 DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
45 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \
46 DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
A Dintel_hti.c20 if (DISPLAY_INFO(display)->has_hti) in intel_hti_init()
A Dintel_display_snapshot.c37 memcpy(&snapshot->info, DISPLAY_INFO(display), sizeof(snapshot->info)); in intel_display_snapshot_capture()
A Dintel_color.c2199 return DISPLAY_INFO(display)->color.gamma_lut_tests; in intel_gamma_lut_tests()
2206 return DISPLAY_INFO(display)->color.degamma_lut_tests; in intel_degamma_lut_tests()
2217 return DISPLAY_INFO(display)->color.gamma_lut_size; in intel_gamma_lut_size()
2224 return DISPLAY_INFO(display)->color.degamma_lut_size; in intel_degamma_lut_size()
2770 DISPLAY_INFO(display)->color.degamma_lut_size, in glk_assign_luts()
3312 u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size; in i9xx_read_lut_10()
3363 int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size; in i965_read_lut_10p6()
3441 int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size; in chv_read_cgm_gamma()
3515 int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size; in ilk_read_lut_10()
3973 gamma_lut_size = DISPLAY_INFO(display)->color.gamma_lut_size; in intel_color_crtc_init()
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A Dintel_display_device.c1661 DISPLAY_INFO(display) = info; in intel_display_device_probe()
1664 &DISPLAY_INFO(display)->__runtime_defaults, in intel_display_device_probe()
1710 DISPLAY_INFO(display) = &no_display; in intel_display_device_probe()
A Dintel_display_driver.c593 intel_display_device_info_print(DISPLAY_INFO(display), in intel_display_driver_register()
A Dintel_display_power.c1087 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1152 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; in icl_mbus_init()
1610 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; in tgl_bw_buddy_init()
A Dintel_display.h86 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
A Dintel_modeset_setup.c335 if (DISPLAY_INFO(display)->color.degamma_lut_size) { in intel_crtc_copy_hw_to_uapi_state()
A Dskl_watermark.c407 return DISPLAY_INFO(display)->dbuf.size / in intel_dbuf_slice_size()
408 hweight8(DISPLAY_INFO(display)->dbuf.slice_mask); in intel_dbuf_slice_size()
427 WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size); in skl_ddb_entry_for_slices()
2578 DISPLAY_INFO(display)->dbuf.slice_mask, in skl_compute_ddb()
A Dintel_cursor.c41 if (DISPLAY_INFO(display)->cursor_needs_physical) in intel_cursor_base()
A Dintel_display_debugfs.c63 intel_display_device_info_print(DISPLAY_INFO(display), in intel_display_caps()
A Dintel_plane.c179 DISPLAY_INFO(display)->cursor_needs_physical; in intel_plane_needs_physical()

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