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Searched refs:DISPLAY_VER (Results 1 – 25 of 86) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_display_device.h146 #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
150 #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
163 #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13)
172 #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
174 #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4)
181 #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12)
184 #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12)
186 #define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12)
196 DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
197 #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
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A Di9xx_display_sr.c20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
45 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_restore_swf()
52 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_restore_swf()
73 if (DISPLAY_VER(display) <= 4) in i9xx_display_sr_save()
76 if (DISPLAY_VER(display) == 4) in i9xx_display_sr_save()
91 if (DISPLAY_VER(display) == 4) in i9xx_display_sr_restore()
95 if (DISPLAY_VER(display) <= 4) in i9xx_display_sr_restore()
A Dintel_psr.c323 if (DISPLAY_VER(display) >= 8) in psr_ctl_reg()
332 if (DISPLAY_VER(display) >= 8) in psr_debug_reg()
341 if (DISPLAY_VER(display) >= 8) in psr_perf_cnt_reg()
350 if (DISPLAY_VER(display) >= 8) in psr_status_reg()
359 if (DISPLAY_VER(display) >= 12) in psr_imr_reg()
368 if (DISPLAY_VER(display) >= 12) in psr_iir_reg()
377 if (DISPLAY_VER(display) >= 8) in psr_aux_ctl_reg()
386 if (DISPLAY_VER(display) >= 8) in psr_aux_data_reg()
1038 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) in hsw_activate_psr2()
1045 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { in hsw_activate_psr2()
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A Dintel_fbc.c176 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
199 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
222 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
285 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
348 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
457 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
662 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
679 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
689 if (DISPLAY_VER(display) >= 20) in ivb_fbc_activate()
1128 if (DISPLAY_VER(display) >= 9) in rotation_is_valid()
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A Di9xx_plane.c217 if (DISPLAY_VER(display) >= 4 && in i9xx_plane_ctl()
260 if (DISPLAY_VER(display) >= 4) in i9xx_check_plane_surface()
375 if (DISPLAY_VER(display) < 5) in i9xx_plane_ctl_crtc()
439 if (DISPLAY_VER(display) < 4) { in i9xx_plane_update_noarm()
477 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
513 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
558 if (DISPLAY_VER(display) >= 4) in i9xx_plane_disable_arm()
747 if (DISPLAY_VER(display) >= 5) in i9xx_plane_get_hw_state()
989 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
1108 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
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A Dintel_wm.c162 if (DISPLAY_VER(display) >= 9) in intel_print_wm_latency()
175 if (DISPLAY_VER(display) >= 9) in intel_wm_init()
195 if (DISPLAY_VER(display) >= 9 || in wm_latency_show()
215 if (DISPLAY_VER(display) >= 9) in pri_wm_latency_show()
230 if (DISPLAY_VER(display) >= 9) in spr_wm_latency_show()
245 if (DISPLAY_VER(display) >= 9) in cur_wm_latency_show()
259 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) in pri_wm_latency_open()
326 if (DISPLAY_VER(display) >= 9) in pri_wm_latency_write()
341 if (DISPLAY_VER(display) >= 9) in spr_wm_latency_write()
356 if (DISPLAY_VER(display) >= 9) in cur_wm_latency_write()
A Dskl_universal_plane.c862 if (DISPLAY_VER(display) < 11) in skl_write_plane_wm()
866 if (DISPLAY_VER(display) >= 30) in skl_write_plane_wm()
1157 if (DISPLAY_VER(display) >= 10) in skl_plane_ctl_crtc()
1195 if (DISPLAY_VER(display) >= 11) in skl_plane_ctl()
1205 if (DISPLAY_VER(display) == 13) in skl_plane_ctl()
1216 if (DISPLAY_VER(display) >= 11) in glk_plane_color_ctl_crtc()
1316 if (DISPLAY_VER(display) < 12) in skl_plane_aux_dist()
1436 if (DISPLAY_VER(display) >= 10) in skl_plane_update_arm()
1457 if (DISPLAY_VER(display) >= 10) in skl_plane_update_arm()
2069 if (DISPLAY_VER(display) >= 13) in skl_check_main_surface()
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A Dintel_display_irq.c286 if (DISPLAY_VER(display) < 5) in i915_pipestat_enable_mask()
393 if (DISPLAY_VER(display) >= 4) in i915_enable_asle_pipestat()
483 if (DISPLAY_VER(display) >= 3) in i9xx_pipe_crc_irq_handler()
979 if (DISPLAY_VER(display) >= 20) in gen8_de_port_aux_mask()
1006 if (DISPLAY_VER(display) >= 9) in gen8_de_port_aux_mask()
1021 if (DISPLAY_VER(display) >= 20) in gen8_de_pipe_fault_mask()
1168 if (DISPLAY_VER(display) >= 14) in gen8_pipe_fault_handlers()
1307 if (DISPLAY_VER(display) >= 9) in gen8_de_pipe_flip_done_mask()
2064 if (DISPLAY_VER(display) >= 14) in gen11_display_irq_reset()
2251 if (DISPLAY_VER(display) < 11) in gen8_de_irq_postinstall()
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A Dintel_ddi.c189 if (DISPLAY_VER(display) >= 14) in intel_ddi_buf_status_reg()
230 if (DISPLAY_VER(display) < 10) { in intel_wait_ddi_buf_active()
520 if (DISPLAY_VER(display) >= 12) in intel_ddi_transcoder_func_reg_val_get()
582 if (DISPLAY_VER(display) >= 14) in intel_ddi_transcoder_func_reg_val_get()
682 if (DISPLAY_VER(display) >= 11) in intel_ddi_disable_transcoder_func()
1046 if (DISPLAY_VER(display) >= 13) in intel_ddi_enable_transcoder_clock()
1065 if (DISPLAY_VER(display) >= 12) in intel_ddi_disable_transcoder_clock()
2425 if (DISPLAY_VER(display) < 30) in intel_ddi_enable_fec()
2487 if (DISPLAY_VER(display) > 20) in intel_ddi_splitter_pipe_mask()
2565 if (DISPLAY_VER(display) < 14) in mtl_ddi_enable_d2d()
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A Dintel_bw.c196 if (DISPLAY_VER(display) >= 14) in icl_pcode_restrict_qgv_points()
248 if (DISPLAY_VER(display) >= 14) in intel_read_qgv_point_info()
796 if (DISPLAY_VER(display) >= 12) in icl_qgv_bw()
865 if (DISPLAY_VER(display) < 11) in intel_bw_crtc_data_rate()
876 if (DISPLAY_VER(display) < 12) in intel_bw_crtc_min_cdclk()
1414 if (DISPLAY_VER(display) < 9) in intel_bw_calc_min_cdclk()
1534 if (DISPLAY_VER(display) < 9) in intel_bw_modeset_checks()
1610 if (DISPLAY_VER(display) < 9) in intel_bw_atomic_check()
1624 if (DISPLAY_VER(display) < 11) in intel_bw_atomic_check()
1676 if (DISPLAY_VER(display) < 9) in intel_bw_update_hw_state()
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A Dintel_cx0_phy_regs.h45 (DISPLAY_VER(i915__) >= 20 ? \
65 (DISPLAY_VER(i915__) >= 20 ? \
96 (DISPLAY_VER(i915__) >= 20 ? \
122 (DISPLAY_VER(i915__) >= 20 ? \
145 (DISPLAY_VER(i915__) >= 20 ? \
168 (DISPLAY_VER(i915__) >= 20 ? \
185 (DISPLAY_VER(i915__) >= 20 ? \
197 #define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \
199 #define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \
202 #define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \
A Dintel_pmdemand.c152 if (DISPLAY_VER(display) < 14) in intel_pmdemand_update_phys_mask()
174 if (DISPLAY_VER(display) < 14) in intel_pmdemand_update_port_clock()
326 if (DISPLAY_VER(display) < 14) in intel_pmdemand_atomic_check()
348 if (DISPLAY_VER(display) < 30) { in intel_pmdemand_atomic_check()
406 if (DISPLAY_VER(display) < 14) in intel_pmdemand_init_pmdemand_params()
435 if (DISPLAY_VER(display) >= 30) { in intel_pmdemand_init_pmdemand_params()
477 if (DISPLAY_VER(display) == 20) { in intel_pmdemand_wait()
495 if (DISPLAY_VER(display) >= 30) in intel_pmdemand_program_dbuf()
559 if (DISPLAY_VER(display) >= 30) { in intel_pmdemand_update_params()
639 if (DISPLAY_VER(display) < 14) in intel_pmdemand_pre_plane_update()
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A Dintel_alpm.c190 if (DISPLAY_VER(display) < 20) in _lnl_compute_alpm_params()
230 if (DISPLAY_VER(display) >= 12) in io_buffer_wake_time()
252 if (DISPLAY_VER(display) >= 20) in intel_alpm_compute_params()
254 else if (DISPLAY_VER(display) >= 12) in intel_alpm_compute_params()
301 if (DISPLAY_VER(display) < 20) in intel_alpm_lobf_compute_config()
341 if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) && in lnl_alpm_configure()
400 if (DISPLAY_VER(display) < 20) in intel_alpm_port_configure()
434 if (DISPLAY_VER(display) < 20) in intel_alpm_pre_plane_update()
575 if (DISPLAY_VER(display) < 20 || in intel_alpm_lobf_debugfs_add()
591 if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd) in intel_alpm_disable()
A Dintel_vrr.c98 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
112 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_flipline_offset()
142 if (DISPLAY_VER(display) >= 13) in intel_vrr_vblank_exit_length()
154 if (DISPLAY_VER(display) >= 13) in intel_vrr_vmin_vtotal()
165 if (DISPLAY_VER(display) >= 13) in intel_vrr_vmax_vtotal()
263 if (DISPLAY_VER(display) >= 13) in intel_vrr_fixed_rr_vtotal()
424 if (DISPLAY_VER(display) >= 13) { in intel_vrr_compute_config_late()
447 if (DISPLAY_VER(display) >= 14) in trans_vrr_ctl()
450 else if (DISPLAY_VER(display) >= 13) in trans_vrr_ctl()
573 if (DISPLAY_VER(display) >= 30) in intel_vrr_always_use_vrr_tg()
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A Dintel_dmc.c447 if (DISPLAY_VER(display) < 12) in disable_all_event_handlers()
659 return DISPLAY_VER(display) == 12; in need_pipedmc_load_program()
669 if (DISPLAY_VER(display) == 30) in need_pipedmc_load_mmio()
678 if (DISPLAY_VER(display) == 20) in need_pipedmc_load_mmio()
745 if (DISPLAY_VER(display) >= 20) { in intel_dmc_enable_pipe()
752 if (DISPLAY_VER(display) >= 14) in intel_dmc_enable_pipe()
768 if (DISPLAY_VER(display) >= 14) in intel_dmc_disable_pipe()
773 if (DISPLAY_VER(display) >= 20) { in intel_dmc_disable_pipe()
866 if (DISPLAY_VER(display) >= 20) in intel_dmc_load_program()
1511 if (DISPLAY_VER(display) < 14) in intel_dmc_get_dc6_allowed_count()
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A Dskl_watermark.c94 return DISPLAY_VER(display) == 9; in skl_needs_memory_bw_wa()
106 if (DISPLAY_VER(display) >= 14) { in intel_sagv_block_time()
143 if (DISPLAY_VER(display) < 11) in intel_sagv_init()
277 if (DISPLAY_VER(display) >= 11) in intel_sagv_pre_plane_update()
297 if (DISPLAY_VER(display) >= 11) in intel_sagv_post_plane_update()
390 if (DISPLAY_VER(display) >= 12) in intel_crtc_can_enable_sagv()
697 if (DISPLAY_VER(display) >= 11) in skl_ddb_get_hw_plane_state()
1844 if (DISPLAY_VER(display) < 30) in skl_compute_plane_wm()
1993 if (DISPLAY_VER(display) == 9) in skl_compute_transition_wm()
3790 if (DISPLAY_VER(display) < 9) in skl_wm_crtc_disable_noatomic()
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A Dintel_display_power.c956 if (DISPLAY_VER(display) >= 20) in get_allowed_dc_mask()
1122 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_enable()
1136 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_disable()
1172 if (DISPLAY_VER(display) == 12) in icl_mbus_init()
1437 if (DISPLAY_VER(display) >= 14) in intel_pch_reset_handshake()
1641 if (DISPLAY_VER(display) == 12) in tgl_bw_buddy_init()
1681 if (DISPLAY_VER(display) == 14) in icl_display_core_init()
1698 if (DISPLAY_VER(display) >= 12) in icl_display_core_init()
1719 if (DISPLAY_VER(display) == 13) in icl_display_core_init()
1750 if (DISPLAY_VER(display) == 14) in icl_display_core_uninit()
[all …]
A Dintel_pch.c52 if (DISPLAY_VER(display) >= 20) in intel_pch_fake_for_south_display()
71 drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5); in intel_pch_type()
76 DISPLAY_VER(display) != 6 && in intel_pch_type()
82 DISPLAY_VER(display) != 6 && in intel_pch_type()
258 else if (DISPLAY_VER(display) == 6 || display->platform.ivybridge) in intel_virt_detect_pch()
260 else if (DISPLAY_VER(display) == 5) in intel_virt_detect_pch()
A Dintel_pfit.c77 if (DISPLAY_VER(display) >= 8) { in intel_pch_pfit_check_src_size()
80 } else if (DISPLAY_VER(display) >= 7) { in intel_pch_pfit_check_src_size()
259 if (DISPLAY_VER(display) >= 9) in pch_panel_fitting()
426 if (DISPLAY_VER(display) >= 4) in intel_gmch_pfit_check_timings()
496 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
510 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
526 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
536 if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
690 return DISPLAY_VER(display) >= 4 || in i9xx_has_pfit()
709 if (DISPLAY_VER(display) >= 4) in i9xx_pfit_get_config()
A Dintel_crtc.c115 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_crtc_max_vblank_count()
117 else if (DISPLAY_VER(display) >= 3) in intel_crtc_max_vblank_count()
320 if (DISPLAY_VER(display) >= 9) in intel_crtc_init()
335 if (DISPLAY_VER(display) >= 9) in intel_crtc_init()
358 else if (DISPLAY_VER(display) == 4) in intel_crtc_init()
363 else if (DISPLAY_VER(display) == 3) in intel_crtc_init()
368 if (DISPLAY_VER(display) >= 8) in intel_crtc_init()
380 if (DISPLAY_VER(display) >= 11) in intel_crtc_init()
678 if (DISPLAY_VER(display) >= 11 && in intel_pipe_update_end()
A Dintel_display.c415 if (DISPLAY_VER(display) >= 4) { in intel_wait_for_pipe_off()
516 if (DISPLAY_VER(display) == 13) in intel_enable_transcoder()
599 if (DISPLAY_VER(display) >= 12) in intel_disable_transcoder()
756 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) in icl_set_pipe_chicken()
841 if (DISPLAY_VER(display) == 9) in needs_nv12_wa()
865 DISPLAY_VER(display) == 11) in needs_cursorclk_wa()
2096 if (DISPLAY_VER(display) != 2) in i9xx_crtc_enable()
2116 if (DISPLAY_VER(display) == 2) in i9xx_crtc_enable()
2132 if (DISPLAY_VER(display) == 2) in i9xx_crtc_disable()
2156 if (DISPLAY_VER(display) != 2) in i9xx_crtc_disable()
[all …]
A Dintel_flipq.c121 if (DISPLAY_VER(display) == 20) in intel_flipq_supported()
125 return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display); in intel_flipq_supported()
140 if (DISPLAY_VER(display) >= 30) in cdclk_factor()
278 if (DISPLAY_VER(display) >= 30) in flipq_event_id()
292 if (DISPLAY_VER(display) >= 30) { in intel_flipq_enable()
437 if (DISPLAY_VER(display) >= 30) in intel_flipq_add()
453 return DISPLAY_VER(display) == 20 || in need_dmc_halt_wa()
A Dskl_scaler.c99 if (DISPLAY_VER(display) >= 14) { in skl_scaler_max_src_size()
102 } else if (DISPLAY_VER(display) >= 12) { in skl_scaler_max_src_size()
105 } else if (DISPLAY_VER(display) == 11) { in skl_scaler_max_src_size()
125 if (DISPLAY_VER(display) >= 12) { in skl_scaler_max_dst_size()
128 } else if (DISPLAY_VER(display) == 11) { in skl_scaler_max_dst_size()
169 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
340 if (DISPLAY_VER(display) >= 14) { in calculate_max_scale()
353 } else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) { in calculate_max_scale()
387 if (DISPLAY_VER(display) == 9) { in intel_atomic_setup_scaler()
405 } else if (DISPLAY_VER(display) >= 10) { in intel_atomic_setup_scaler()
[all …]
A Dintel_audio.c522 if (DISPLAY_VER(display) < 11) in enable_audio_dsc_wa()
527 if (DISPLAY_VER(display) == 11) in enable_audio_dsc_wa()
913 if (DISPLAY_VER(display) >= 13) in intel_audio_cdclk_change_pre()
927 if (DISPLAY_VER(display) >= 13) { in intel_audio_cdclk_change_post()
1012 if (DISPLAY_VER(display) == 10) { in intel_audio_min_cdclk()
1025 if (DISPLAY_VER(display) >= 9) in intel_audio_min_cdclk()
1053 if (DISPLAY_VER(display) >= 9) { in intel_audio_component_get_power()
1065 if (DISPLAY_VER(display) >= 10) in intel_audio_component_get_power()
1093 if (DISPLAY_VER(display) < 9) in intel_audio_component_codec_wake_override()
1337 if (DISPLAY_VER(display) >= 9) { in intel_audio_component_init()
[all …]
A Dintel_sprite_uapi.c13 return DISPLAY_VER(display) >= 9; in has_dst_key_in_primary_plane()
37 if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_PRIMARY && in intel_plane_set_ckey()
76 if (DISPLAY_VER(display) >= 9 && in intel_sprite_set_colorkey_ioctl()

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