Searched refs:DMA0_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| A D | ni_dma.c | 61 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_rptr()
85 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_wptr()
106 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_set_wptr()
165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
197 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
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| A D | ni.c | 844 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in cayman_get_allowed_info_register()
1106 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1743 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()
1824 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
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| A D | si.c | 1297 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in si_get_allowed_info_register()
3782 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3864 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3866 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4031 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4033 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5519 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5531 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5938 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5939 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
[all …]
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| A D | nid.h | 1301 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| A D | sid.h | 1812 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | si_dma.c | 34 DMA0_REGISTER_OFFSET,
602 sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
604 WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
607 sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
609 WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
661 offset = DMA0_REGISTER_OFFSET; in si_dma_set_clockgating_state()
673 offset = DMA0_REGISTER_OFFSET; in si_dma_set_clockgating_state()
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| A D | sid.h | 553 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| A D | si.c | 1133 {mmDMA_STATUS_REG + DMA0_REGISTER_OFFSET},
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| A D | gfx_v6_0.c | 1719 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_constants_init()
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