Searched refs:DMA1_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| A D | ni_dma.c | 63 reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_rptr()
87 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_wptr()
108 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_set_wptr()
170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
201 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
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| A D | ni.c | 845 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in cayman_get_allowed_info_register()
1107 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1748 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()
1831 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1833 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
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| A D | si.c | 1298 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in si_get_allowed_info_register()
3787 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3870 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3872 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4035 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4037 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5521 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()
5533 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()
5940 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5941 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
[all …]
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| A D | nid.h | 1302 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
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| A D | sid.h | 1813 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | si_dma.c | 35 DMA1_REGISTER_OFFSET
618 sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
620 WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
623 sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
625 WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
663 offset = DMA1_REGISTER_OFFSET; in si_dma_set_clockgating_state()
675 offset = DMA1_REGISTER_OFFSET; in si_dma_set_clockgating_state()
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| A D | sid.h | 554 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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| A D | si.c | 1134 {mmDMA_STATUS_REG + DMA1_REGISTER_OFFSET},
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| A D | gfx_v6_0.c | 1720 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_constants_init()
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