Searched refs:DMA_CH_SR (Results 1 – 6 of 6) sorted by relevance
| /drivers/net/ethernet/amd/xgbe/ |
| A D | xgbe-drv.c | 392 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); in xgbe_isr_bh_work()
401 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || in xgbe_isr_bh_work()
402 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { in xgbe_isr_bh_work()
415 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); in xgbe_isr_bh_work()
416 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); in xgbe_isr_bh_work()
419 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) in xgbe_isr_bh_work()
423 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) in xgbe_isr_bh_work()
427 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); in xgbe_isr_bh_work()
528 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); in xgbe_dma_isr()
529 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); in xgbe_dma_isr()
[all …]
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| A D | xgbe-common.h | 97 #define DMA_CH_SR 0x60 macro
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| A D | xgbe-dev.c | 578 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, in xgbe_enable_dma_interrupts()
579 XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); in xgbe_enable_dma_interrupts()
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| /drivers/net/ethernet/synopsys/ |
| A D | dwc-xlgmac-reg.h | 553 #define DMA_CH_SR 0x60 macro
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| A D | dwc-xlgmac-net.c | 277 dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR)); in xlgmac_isr()
324 writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR)); in xlgmac_isr()
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| A D | dwc-xlgmac-hw.c | 2455 dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR)); in xlgmac_enable_dma_interrupts()
2456 writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR)); in xlgmac_enable_dma_interrupts()
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