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Searched refs:DML2_MAX_DCN_PIPES (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h330 bool unoptimizable_streams[DML2_MAX_DCN_PIPES];
762 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];
763 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];
766 …struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One s…
771 …struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pi…
939 int pipe_vp_startx[DML2_MAX_DCN_PIPES];
940 int pipe_vp_endx[DML2_MAX_DCN_PIPES];
943 int pipe_vp_startx[DML2_MAX_DCN_PIPES];
944 int pipe_vp_endx[DML2_MAX_DCN_PIPES];
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_display_cfg_types.h11 #define DML2_MAX_DCN_PIPES 8 macro
505 struct dml2_pipe_configuration_descriptor pipe_configurations[DML2_MAX_DCN_PIPES];
A Ddml_top_types.h721 struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];
724 struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES];
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c392 for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { in map_min_clocks_to_dpm()
619 for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { in map_mode_to_soc_dpm()
626 for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { in map_mode_to_soc_dpm()
647 for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { in map_mode_to_soc_dpm()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c1025 …memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct… in dml2_top_soc15_build_mcache_programming()

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