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Searched refs:DML2_MAX_MCACHES (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_types.h150 int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];
151 int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];
166 int global_mcache_ids_plane0[DML2_MAX_MCACHES + 1];
167 int global_mcache_ids_plane1[DML2_MAX_MCACHES + 1];
168 int global_mcache_ids_mall_plane0[DML2_MAX_MCACHES + 1];
169 int global_mcache_ids_mall_plane1[DML2_MAX_MCACHES + 1];
A Ddml_top_display_cfg_types.h12 #define DML2_MAX_MCACHES 8 // assume plane is going to be supported by a max of 8 mcaches macro
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.h132 int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];
133 int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];
A Ddml21_wrapper.c195 sizeof(int) * (DML2_MAX_MCACHES + 1)); in dml21_prepare_mcache_params()
198 sizeof(int) * (DML2_MAX_MCACHES + 1)); in dml21_prepare_mcache_params()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_shared_types.h590 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
596 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
994 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
1000 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

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