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Searched refs:DML2_MAX_PLANES (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_shared_types.h284 double OutputBpp[DML2_MAX_PLANES];
401 double TWait[DML2_MAX_PLANES];
454 double Tno_bw[DML2_MAX_PLANES];
510 double TSetup[DML2_MAX_PLANES];
567 bool MPCCombine[DML2_MAX_PLANES];
711 double Tno_bw[DML2_MAX_PLANES];
764 double TWait[DML2_MAX_PLANES];
766 double Tdmdl_vm[DML2_MAX_PLANES];
768 double Tdmdl[DML2_MAX_PLANES];
769 double TSetup[DML2_MAX_PLANES];
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A Ddml2_core_utils.c403 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml2_core_utils_pipe_plane_mapping()
407 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml2_core_utils_pipe_plane_mapping()
617 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
618 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
619 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
A Ddml2_core_dcn4.c198 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
199 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
200 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
A Ddml2_core_dcn4_calcs.c221 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml_calc_pipe_plane_mapping()
1028 bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES]; in CalculateDETBufferSize()
3506 double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleepTdlut()
3595 double zero_double[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleep()
3596 unsigned int zero_integer[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleep()
3598 memset(zero_double, 0, DML2_MAX_PLANES * sizeof(double)); in CalculateDCFCLKDeepSleep()
3684 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3685 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
12357 DML_ASSERT(l->plane_idx < DML2_MAX_PLANES); in rq_dlg_get_dlg_reg()
12371 if (l->plane_idx < DML2_MAX_PLANES) { in rq_dlg_get_dlg_reg()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_types.h353 double OutputBpp[DML2_MAX_PLANES];
356 unsigned int AlignedYPitch[DML2_MAX_PLANES];
459 } plane_info[DML2_MAX_PLANES];
587 } dcc_control[DML2_MAX_PLANES];
634 double Tdmdl_vm[DML2_MAX_PLANES];
635 double Tdmdl[DML2_MAX_PLANES];
636 unsigned int VStartup[DML2_MAX_PLANES];
649 double VRatioPrefetchY[DML2_MAX_PLANES];
650 double VRatioPrefetchC[DML2_MAX_PLANES];
666 bool PTE_BUFFER_MODE[DML2_MAX_PLANES];
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A Ddml_top_display_cfg_types.h10 #define DML2_MAX_PLANES 8 macro
440 struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];
441 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h218 } per_stream[DML2_MAX_PLANES];
224 } per_plane[DML2_MAX_PLANES];
243 bool per_plane_mcache_support[DML2_MAX_PLANES];
627 int current_candidate[DML2_MAX_PLANES];
640 unsigned int stream_plane_mask[DML2_MAX_PLANES];
661 bool group_is_drr_enabled[DML2_MAX_PLANES];
662 bool group_is_drr_active[DML2_MAX_PLANES];
663 double group_line_time_us[DML2_MAX_PLANES];
669 double group_phase_offset[DML2_MAX_PLANES];
748 bool per_plane_status[DML2_MAX_PLANES];
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/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h564 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];
566 union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES];
568 union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES];
569 union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES];
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
A Ddml2_pmo_dcn4_fams2.c550 enum dml2_pstate_method per_stream_variant_method[DML2_MAX_PLANES]; in expand_variant_strategy()
1043 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_timings_support_drr()
1088 unsigned int num_planes_per_stream[DML2_MAX_PLANES] = { 0 }; in all_timings_support_svp()
1124 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_timings_support_svp()
1223 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_planes_match_method()
1358 memset(s->pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES); in is_config_schedulable()
1639 for (i = 0; i < DML2_MAX_PLANES; i++) { in get_vactive_pstate_margin()
1654 for (i = 0; i < DML2_MAX_PLANES; i++) { in get_vactive_det_fill_latency_delay_us()
2149 sizeof(struct dml2_fams2_meta) * DML2_MAX_PLANES); in setup_display_config()
A Ddml2_pmo_dcn3.c201 unsigned int remap_array[DML2_MAX_PLANES]; in are_timings_trivially_synchronizable()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_utils.c385 …>bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); in dml21_build_fams2_programming()
386 …->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); in dml21_build_fams2_programming()
387 …s2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES); in dml21_build_fams2_programming()
A Ddml21_wrapper.c113 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { in dml21_calculate_rq_and_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c420 unsigned int remap_array[DML2_MAX_PLANES]; in are_timings_trivially_synchronizable()
458 unsigned int remap_array[DML2_MAX_PLANES]; in find_smallest_idle_time_in_vblank_us()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c85 …rt, l->test_mcache.validate_admissibility_params.per_plane_status, sizeof(bool) * DML2_MAX_PLANES); in dml2_top_optimization_test_function_mcache()
1025 …memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct… in dml2_top_soc15_build_mcache_programming()

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