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Searched refs:DML_MAX_CLK_TABLE_SIZE (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_soc_parameter_types.h10 #define DML_MAX_CLK_TABLE_SIZE 20 macro
66 struct dml2_dcn4_uclk_dpm_dependent_qos_params per_uclk_dpm_params[DML_MAX_CLK_TABLE_SIZE];
102 double g6_temp_read_blackout_us[DML_MAX_CLK_TABLE_SIZE];
108 unsigned long clk_values_khz[DML_MAX_CLK_TABLE_SIZE];
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c102 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
125 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
148 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
171 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
194 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
217 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
240 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in override_dml_init_with_values_from_smu()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_utils.c513 for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { in dml2_core_utils_get_qos_param_index()
A Ddml2_core_dcn4_calcs.c7083 for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { in get_qos_param_index()
7171 } entries[DML_MAX_CLK_TABLE_SIZE];
7227 for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { in get_g6_temp_read_blackout_us()

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