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Searched refs:DP (Results 1 – 25 of 71) sorted by relevance

123

/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_link_encoder.h54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
58 SRI(DP_DPHY_SYM0, DP, id), \
64 SRI(DP_MSE_SAT0, DP, id), \
65 SRI(DP_MSE_SAT1, DP, id), \
66 SRI(DP_MSE_SAT2, DP, id), \
68 SRI(DP_SEC_CNTL, DP, id), \
71 SRI(DP_SEC_CNTL1, DP, id)
88 SRI(DP_CONFIG, DP, id), \
97 SRI(DP_MSE_SAT0, DP, id), \
[all …]
A Ddce_stream_encoder.h84 SRI(DP_MSE_RATE_CNTL, DP, id), \
86 SRI(DP_PIXEL_FORMAT, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_STEER_FIFO, DP, id), \
89 SRI(DP_VID_M, DP, id), \
90 SRI(DP_VID_N, DP, id), \
92 SRI(DP_VID_TIMING, DP, id), \
93 SRI(DP_SEC_AUD_N, DP, id), \
94 SRI(DP_SEC_TIMESTAMP, DP, id)
106 SRI(DP_DB_CNTL, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn301/
A Ddcn301_dio_link_encoder.h37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
43 SRI(DP_DPHY_SYM2, DP, id), \
45 SRI(DP_LINK_CNTL, DP, id), \
47 SRI(DP_MSE_SAT0, DP, id), \
48 SRI(DP_MSE_SAT1, DP, id), \
49 SRI(DP_MSE_SAT2, DP, id), \
51 SRI(DP_SEC_CNTL, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_link_encoder.h36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
42 SRI(DP_DPHY_SYM2, DP, id), \
44 SRI(DP_LINK_CNTL, DP, id), \
46 SRI(DP_MSE_SAT0, DP, id), \
47 SRI(DP_MSE_SAT1, DP, id), \
48 SRI(DP_MSE_SAT2, DP, id), \
50 SRI(DP_SEC_CNTL, DP, id), \
[all …]
A Ddcn30_dio_stream_encoder.h76 SRI(DP_DB_CNTL, DP, id), \
77 SRI(DP_MSA_MISC, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_SEC_CNTL1, DP, id), \
89 SRI(DP_SEC_CNTL2, DP, id), \
90 SRI(DP_SEC_CNTL5, DP, id), \
91 SRI(DP_SEC_CNTL6, DP, id), \
93 SRI(DP_VID_M, DP, id), \
94 SRI(DP_VID_N, DP, id), \
97 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/drivers/gpu/drm/i915/display/
A Dg4x_dp.c135 intel_dp->DP |= DP_SYNC_HS_HIGH; in intel_dp_prepare()
137 intel_dp->DP |= DP_SYNC_VS_HIGH; in intel_dp_prepare()
156 intel_dp->DP |= DP_SYNC_HS_HIGH; in intel_dp_prepare()
228 intel_dp->DP |= EDP_PLL_ENABLE; in ilk_edp_pll_on()
246 intel_dp->DP &= ~EDP_PLL_ENABLE; in ilk_edp_pll_off()
438 intel_dp->DP &= ~DP_PORT_EN; in intel_dp_link_down()
462 intel_dp->DP &= ~DP_PORT_EN; in intel_dp_link_down()
658 intel_dp->DP |= DP_PORT_EN; in intel_dp_enable_port()
1031 intel_dp->DP |= signal_levels; in g4x_set_signal_levels()
1079 intel_dp->DP |= signal_levels; in snb_cpu_edp_set_signal_levels()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h108 SRI_ARR(DP_DB_CNTL, DP, id), \
109 SRI_ARR(DP_MSA_MISC, DP, id), \
119 SRI_ARR(DP_SEC_CNTL, DP, id), \
120 SRI_ARR(DP_SEC_CNTL1, DP, id), \
121 SRI_ARR(DP_SEC_CNTL2, DP, id), \
122 SRI_ARR(DP_SEC_CNTL5, DP, id), \
123 SRI_ARR(DP_SEC_CNTL6, DP, id), \
125 SRI_ARR(DP_VID_M, DP, id), \
126 SRI_ARR(DP_VID_N, DP, id), \
129 SRI_ARR(DP_SEC_AUD_N, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.h77 SRI(DP_DB_CNTL, DP, id), \
78 SRI(DP_MSA_MISC, DP, id), \
88 SRI(DP_SEC_CNTL, DP, id), \
89 SRI(DP_SEC_CNTL1, DP, id), \
90 SRI(DP_SEC_CNTL2, DP, id), \
91 SRI(DP_SEC_CNTL5, DP, id), \
92 SRI(DP_SEC_CNTL6, DP, id), \
94 SRI(DP_VID_M, DP, id), \
95 SRI(DP_VID_N, DP, id), \
98 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.h75 SRI(DP_DB_CNTL, DP, id), \
76 SRI(DP_MSA_MISC, DP, id), \
86 SRI(DP_SEC_CNTL, DP, id), \
87 SRI(DP_SEC_CNTL1, DP, id), \
88 SRI(DP_SEC_CNTL2, DP, id), \
89 SRI(DP_SEC_CNTL5, DP, id), \
90 SRI(DP_SEC_CNTL6, DP, id), \
92 SRI(DP_VID_M, DP, id), \
93 SRI(DP_VID_N, DP, id), \
96 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_ethtool.c409 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
418 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
498 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
1949 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_ringparam()
1954 DP(BNX2X_MSG_IOV, in bnx2x_set_ringparam()
1960 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_ringparam()
2049 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_pauseparam()
3015 DP(BNX2X_MSG_IOV, in bnx2x_self_test()
3027 DP(BNX2X_MSG_ETHTOOL, in bnx2x_self_test()
3380 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_rxfh_fields()
[all …]
A Dbnx2x_dcb.c134 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
137 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
141 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
160 DP(BNX2X_MSG_DCB, in bnx2x_dump_dcbx_drv_param()
163 DP(BNX2X_MSG_DCB, in bnx2x_dump_dcbx_drv_param()
166 DP(BNX2X_MSG_DCB, in bnx2x_dump_dcbx_drv_param()
256 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_get_ap_feature()
365 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_map_nw()
1080 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_print_cos_params()
1082 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_print_cos_params()
[all …]
A Dbnx2x_link.c750 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_disabled()
923 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_get_total_bw()
927 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_get_total_bw()
1146 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1164 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1198 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1203 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1214 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1661 DP(NETIF_MSG_LINK, in bnx2x_xmac_init()
7217 DP(NETIF_MSG_LINK, in bnx2x_8073_8727_external_rom_boot()
[all …]
A Dbnx2x_sriov.c131 DP(BNX2X_MSG_IOV, in bnx2x_vfop_qctor_dump_tx()
736 DP(BNX2X_MSG_IOV, in bnx2x_vf_igu_reset()
964 DP(BNX2X_MSG_MCP, in bnx2x_vf_handle_flr_event()
983 DP(BNX2X_MSG_IOV, in bnx2x_vf_handle_flr_event()
1159 DP(BNX2X_MSG_IOV, in bnx2x_sriov_info()
1434 DP(BNX2X_MSG_IOV, in bnx2x_vfq_init()
1566 DP(BNX2X_MSG_IOV, in bnx2x_iov_nic_init()
1618 DP(BNX2X_MSG_IOV, in bnx2x_iov_nic_init()
2047 DP(BNX2X_MSG_IOV, in bnx2x_vf_acquire()
2058 DP(BNX2X_MSG_IOV, in bnx2x_vf_acquire()
[all …]
A Dbnx2x_main.c1604 DP(NETIF_MSG_IFUP, in bnx2x_hc_int_enable()
1822 DP(BNX2X_MSG_SP, in bnx2x_sp_event()
2601 DP(NETIF_MSG_IFUP, in bnx2x_cmng_fns_init()
2818 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
2826 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
2839 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
2857 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
3944 DP(BNX2X_MSG_SP, in bnx2x_sp_post()
5225 DP(NETIF_MSG_HW, in bnx2x_attn_int()
5372 DP(BNX2X_MSG_SP, in bnx2x_after_afex_vif_lists()
[all …]
A Dbnx2x_sp.c131 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); in bnx2x_exe_queue_add()
1703 DP(BNX2X_MSG_SP, "Optimizing %s command\n", in bnx2x_optimize_vlan_mac()
2884 DP(BNX2X_MSG_SP, "%s bin %d\n", in bnx2x_mcast_set_one_rule_e2()
3550 DP(BNX2X_MSG_SP, in bnx2x_mcast_setup_e1h()
3869 DP(BNX2X_MSG_SP, "Deleting a registry\n"); in bnx2x_mcast_refresh_registry_e1()
4460 DP(BNX2X_MSG_SP, "0x0000: "); in bnx2x_debug_print_ind_table()
4468 DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); in bnx2x_debug_print_ind_table()
4496 DP(BNX2X_MSG_SP, "Configuring RSS\n"); in bnx2x_setup_rss()
4755 DP(BNX2X_MSG_SP, in bnx2x_queue_comp_cmd()
5759 DP(BNX2X_MSG_SP, in bnx2x_func_state_change_comp()
[all …]
A Dbnx2x_vfpf.c299 DP(BNX2X_MSG_SP, in bnx2x_vfpf_acquire()
427 DP(BNX2X_MSG_SP, "vf released\n"); in bnx2x_vfpf_release()
768 DP(BNX2X_MSG_IOV, in bnx2x_vfpf_config_mac()
858 DP(BNX2X_MSG_IOV, in bnx2x_vfpf_config_rss()
890 DP(NETIF_MSG_IFUP, in bnx2x_vfpf_set_mcast()
1406 DP(BNX2X_MSG_IOV, in bnx2x_vf_mbx_acquire()
1420 DP(BNX2X_MSG_IOV, in bnx2x_vf_mbx_acquire()
1435 DP(BNX2X_MSG_IOV, in bnx2x_vf_mbx_acquire()
2117 DP(BNX2X_MSG_IOV, in bnx2x_vf_mbx_request()
2197 DP(BNX2X_MSG_IOV, in bnx2x_vf_mbx_schedule()
[all …]
A Dbnx2x_cmn.c296 DP(NETIF_MSG_TX_DONE, in bnx2x_tx_int()
402 DP(NETIF_MSG_RX_STATUS, in bnx2x_update_sge_prod()
835 DP(NETIF_MSG_RX_STATUS, in bnx2x_tpa_stop()
920 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
1146 DP(NETIF_MSG_INTR, in bnx2x_msix_fp_int()
1421 DP(NETIF_MSG_IFUP, in bnx2x_init_rx_rings()
2632 DP(NETIF_MSG_IFUP, in bnx2x_nic_load()
4417 DP(NETIF_MSG_IFDOWN, in bnx2x_free_fp_mem_at()
4581 DP(NETIF_MSG_IFUP, in bnx2x_alloc_fp_mem_at()
5097 DP(NETIF_MSG_IFUP, in storm_memset_hc_timeout()
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.h47 SRI(DP_CONFIG, DP, id), \
48 SRI(DP_DPHY_CNTL, DP, id), \
51 SRI(DP_DPHY_SYM0, DP, id), \
52 SRI(DP_DPHY_SYM1, DP, id), \
53 SRI(DP_DPHY_SYM2, DP, id), \
55 SRI(DP_LINK_CNTL, DP, id), \
57 SRI(DP_MSE_SAT0, DP, id), \
58 SRI(DP_MSE_SAT1, DP, id), \
59 SRI(DP_MSE_SAT2, DP, id), \
61 SRI(DP_SEC_CNTL, DP, id), \
[all …]
A Ddcn10_stream_encoder.h74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
85 SRI(DP_SEC_CNTL, DP, id), \
86 SRI(DP_SEC_CNTL1, DP, id), \
87 SRI(DP_SEC_CNTL2, DP, id), \
88 SRI(DP_SEC_CNTL5, DP, id), \
89 SRI(DP_SEC_CNTL6, DP, id), \
90 SRI(DP_STEER_FIFO, DP, id), \
91 SRI(DP_VID_M, DP, id), \
92 SRI(DP_VID_N, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h287 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
288 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
293 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
294 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
295 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
296 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
297 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \
298 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
299 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
300 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h198 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
199 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
204 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
205 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
206 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
207 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
208 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \
209 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
210 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
214 SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \
[all …]
/drivers/gpu/drm/bridge/cadence/
A DKconfig25 tristate "Cadence DPI/DP bridge"
33 Support Cadence DPI to DP bridge. This is an internal
36 in DP format.
42 bool "J721E Cadence DPI/DP wrapper support"
45 Support J721E Cadence DPI/DP wrapper. This is a wrapper
/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c256 uint32_t DP; member
1472 uint32_t DP = intel_dp->DP; in cdv_intel_dp_start_link_train() local
1474 DP |= DP_PORT_EN; in cdv_intel_dp_start_link_train()
1475 DP &= ~DP_LINK_TRAIN_MASK; in cdv_intel_dp_start_link_train()
1477 reg = DP; in cdv_intel_dp_start_link_train()
1496 reg = DP | DP_LINK_TRAIN_PAT_1; in cdv_intel_dp_start_link_train()
1552 intel_dp->DP = DP; in cdv_intel_dp_start_link_train()
1562 uint32_t DP = intel_dp->DP; in cdv_intel_dp_complete_link_train() local
1630 reg = DP | DP_LINK_TRAIN_OFF; in cdv_intel_dp_complete_link_train()
1643 uint32_t DP = intel_dp->DP; in cdv_intel_dp_link_down() local
[all …]
/drivers/gpu/drm/display/
A DKconfig36 bool "DRM DP AUX Interface"
40 read and write values to arbitrary DPCD registers on the DP aux
53 DP tunnel features like the Bandwidth Allocation mode to maximize the
57 bool "Enable debugging the DP tunnel state"
63 Enables debugging the DP tunnel manager's state, including the
/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_stream_encoder.h37 SRI(DP_DSC_CNTL, DP, id), \
38 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
40 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
42 SRI(DP_SEC_FRAMING4, DP, id)

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