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Searched refs:DPIO_CH0 (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c1181 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0)); in iterate_bxt_mmio()
1182 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1)); in iterate_bxt_mmio()
1183 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2)); in iterate_bxt_mmio()
1184 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3)); in iterate_bxt_mmio()
1185 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6)); in iterate_bxt_mmio()
1186 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8)); in iterate_bxt_mmio()
1187 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9)); in iterate_bxt_mmio()
1231 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0)); in iterate_bxt_mmio()
1232 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1)); in iterate_bxt_mmio()
1233 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2)); in iterate_bxt_mmio()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_display_power_well.c1364 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1365 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1372 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1373 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1387 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1389 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1402 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) in assert_chv_phy_status()
1405 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) in assert_chv_phy_status()
1425 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); in assert_chv_phy_status()
1563 if (ch == DPIO_CH0) in assert_chv_phy_powergate()
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A Dintel_dpio_phy.c176 [DPIO_CH0] = { .port = PORT_B },
186 [DPIO_CH0] = { .port = PORT_A },
199 [DPIO_CH0] = { .port = PORT_B },
209 [DPIO_CH0] = { .port = PORT_A },
219 [DPIO_CH0] = { .port = PORT_C },
259 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
274 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
667 return DPIO_CH0; in vlv_dig_port_to_channel()
709 return DPIO_CH0; in vlv_pipe_to_channel()
899 if (ch == DPIO_CH0) in chv_phy_pre_pll_enable()
[all …]
A Dintel_dpio_phy.h19 DPIO_CH0, enumerator
116 return DPIO_CH0; in vlv_dig_port_to_channel()
128 return DPIO_CH0; in vlv_pipe_to_channel()
A Dintel_display_power.c1785 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init()
1787 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1805 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1808 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1837 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1840 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
A Dintel_dpll_mgr.c2047 enum dpio_channel ch = DPIO_CH0; in bxt_ddi_pll_enable()
/drivers/gpu/drm/i915/gvt/
A Dhandlers.c554 enum dpio_channel ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
562 ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
566 ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
2792 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2794 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()
2800 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2802 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()

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