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Searched refs:DPIO_PHY0 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c1138 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY0)); in iterate_bxt_mmio()
1146 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0)); in iterate_bxt_mmio()
1147 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0)); in iterate_bxt_mmio()
1148 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0)); in iterate_bxt_mmio()
1149 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0)); in iterate_bxt_mmio()
1150 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0)); in iterate_bxt_mmio()
1151 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0)); in iterate_bxt_mmio()
1152 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0)); in iterate_bxt_mmio()
1153 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0)); in iterate_bxt_mmio()
1154 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0)); in iterate_bxt_mmio()
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/drivers/gpu/drm/i915/display/
A Dintel_display_power_well.c1362 if (!display->power.chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1364 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1365 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1366 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1367 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1368 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1376 phy_status |= PHY_POWERGOOD(DPIO_PHY0); in assert_chv_phy_status()
1389 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1399 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1463 phy = DPIO_PHY0; in chv_dpio_cmn_power_well_enable()
[all …]
A Dintel_dpio_phy.h24 DPIO_PHY0, enumerator
120 return DPIO_PHY0; in vlv_dig_port_to_phy()
124 return DPIO_PHY0; in vlv_pipe_to_phy()
A Dintel_dpio_phy.c170 [DPIO_PHY0] = {
192 [DPIO_PHY0] = {
273 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
681 return DPIO_PHY0; in vlv_dig_port_to_phy()
695 return DPIO_PHY0; in vlv_pipe_to_phy()
886 !chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
1032 chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
A Dintel_display_power.c1783 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | in chv_phy_control_init()
1785 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init()
1786 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | in chv_phy_control_init()
1805 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1808 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1815 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1818 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1820 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1822 display->power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1824 display->power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
A Dvlv_sideband.c19 return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO; in vlv_dpio_phy_to_unit()
A Dintel_display_power_map.c481 .bxt.phy = DPIO_PHY0,
584 .bxt.phy = DPIO_PHY0,
A Dintel_display_regs.h178 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
A Dintel_dpll_mgr.c2046 enum dpio_phy phy = DPIO_PHY0; in bxt_ddi_pll_enable()
/drivers/gpu/drm/i915/gvt/
A Ddisplay.c247 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
251 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
311 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
313 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
342 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
344 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
A Dmmio.c267 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
A Dhandlers.c553 enum dpio_phy phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
565 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
569 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
1900 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in bxt_gt_disp_pwron_write()
1902 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in bxt_gt_disp_pwron_write()
2781 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, in init_bxt_mmio_info()
2792 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2794 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()
2796 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
2798 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT, in init_bxt_mmio_info()

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