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Searched refs:DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/gma500/
A Dpsb_intel_display.c176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
A Dpsb_intel_reg.h237 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro
/drivers/gpu/drm/i915/display/
A Dintel_dpll.c458 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
1043 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_dpll()
1315 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_dpll()
A Dintel_display_regs.h148 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro

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