Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 6 of 6) sorted by relevance
454 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()485 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()496 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in i9xx_crtc_clock_get()1031 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()1037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()1102 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()1107 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()1309 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
187 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
8236 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
344 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()360 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
875 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()895 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
254 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
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