Searched refs:DPLL_VCO_ENABLE (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| A D | oaktrail_crtc.c | 246 if ((temp & DPLL_VCO_ENABLE) == 0) { in oaktrail_crtc_dpms()
252 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
257 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
318 if ((temp & DPLL_VCO_ENABLE) != 0) { in oaktrail_crtc_dpms()
320 temp & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
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| A D | gma_display.c | 224 if ((temp & DPLL_VCO_ENABLE) == 0) { in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
312 if ((temp & DPLL_VCO_ENABLE) != 0) { in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
633 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in gma_crtc_restore()
635 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
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| A D | psb_intel_display.c | 209 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()
218 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
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| A D | cdv_intel_display.c | 758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
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| A D | psb_intel_reg.h | 229 #define DPLL_VCO_ENABLE (1 << 31) macro
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_dpll.c | 527 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
555 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
1009 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i9xx_dpll()
1099 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i8xx_dpll()
1273 dpll = DPLL_VCO_ENABLE; in ilk_dpll()
1434 dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; in vlv_dpll()
1460 dpll |= DPLL_VCO_ENABLE; in chv_dpll()
2011 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2013 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2157 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
[all …]
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| A D | intel_pch_refclk.c | 539 if (!(temp & DPLL_VCO_ENABLE)) in ilk_init_pch_refclk()
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| A D | intel_display_power_well.c | 1398 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
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| A D | intel_pps.c | 129 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
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| A D | intel_display_regs.h | 137 #define DPLL_VCO_ENABLE (1 << 31) macro
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| A D | intel_dpll_mgr.c | 549 return val & DPLL_VCO_ENABLE; in ibx_pch_dpll_get_hw_state()
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| A D | intel_display.c | 8239 DPLL_VCO_ENABLE; in i830_enable_pipe()
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