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Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_dpll.c1009 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i9xx_dpll()
1099 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i8xx_dpll()
1427 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_dpll()
1453 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_dpll()
1845 hw_state->dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
2183 DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
2237 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_disable_pll()
2255 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()
2285 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
A Dintel_display_power_well.c1243 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
A Dintel_display.c8235 DPLL_VGA_MODE_DIS | in i830_enable_pipe()
8265 dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
8315 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
A Dintel_display_regs.h143 #define DPLL_VGA_MODE_DIS (1 << 28) macro
/drivers/gpu/drm/gma500/
A Dcdv_intel_display.c227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
A Dpsb_intel_display.c158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
A Doaktrail_crtc.c527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
A Dpsb_intel_reg.h232 #define DPLL_VGA_MODE_DIS (1 << 28) macro

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