Searched refs:DPU_CLK_CTRL_REG_DMA (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/msm/disp/dpu1/catalog/ |
| A D | dpu_6_4_sm6350.h | 30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_6_0_sm8250.h | 33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_7_0_sm8350.h | 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_9_0_sm8550.h | 25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_9_1_sar2130p.h | 25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_10_0_sm8650.h | 25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_8_0_sc8280xp.h | 33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_8_1_sm8450.h | 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_9_2_x1e80100.h | 24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_8_4_sa8775p.h | 33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| A D | dpu_12_0_sm8750.h | 26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_catalog.h | 360 DPU_CLK_CTRL_REG_DMA, enumerator
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