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Searched refs:DPU_IRQ_MASK (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_interrupts.c202 #define DPU_IRQ_MASK(irq_idx) (BIT(DPU_IRQ_BIT(irq_idx))) macro
338 if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) { in dpu_hw_intr_enable_irq_locked()
343 cache_irq_mask |= DPU_IRQ_MASK(irq_idx); in dpu_hw_intr_enable_irq_locked()
345 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_enable_irq_locked()
357 DPU_IRQ_MASK(irq_idx), cache_irq_mask); in dpu_hw_intr_enable_irq_locked()
390 if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) { in dpu_hw_intr_disable_irq_locked()
395 cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx); in dpu_hw_intr_disable_irq_locked()
399 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_disable_irq_locked()
409 DPU_IRQ_MASK(irq_idx), cache_irq_mask); in dpu_hw_intr_disable_irq_locked()
477 DPU_IRQ_MASK(irq_idx); in dpu_core_irq_read()

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