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Searched refs:DPU_REG_READ (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_vbif.c46 pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR); in dpu_hw_clear_errors()
47 src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR); in dpu_hw_clear_errors()
81 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
102 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
124 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_get_limit_conf()
136 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0); in dpu_hw_set_halt_ctrl()
152 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1); in dpu_hw_get_halt_ctrl()
172 reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high); in dpu_hw_set_qos_remap()
173 reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high); in dpu_hw_set_qos_remap()
197 reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN); in dpu_hw_set_write_gather_en()
A Ddpu_hw_intf.c119 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
276 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_prg_fetch()
295 mux_cfg = DPU_REG_READ(c, INTF_MUX); in dpu_hw_intf_bind_pingpong_blk()
313 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); in dpu_hw_intf_get_status()
315 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); in dpu_hw_intf_get_status()
320 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); in dpu_hw_intf_get_status()
336 return DPU_REG_READ(c, INTF_LINE_COUNT); in dpu_hw_intf_get_line_count()
461 val = DPU_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL); in dpu_hw_intf_get_vsync_info()
464 val = DPU_REG_READ(c, INTF_TEAR_INT_COUNT_VAL); in dpu_hw_intf_get_vsync_info()
468 val = DPU_REG_READ(c, INTF_TEAR_LINE_COUNT); in dpu_hw_intf_get_vsync_info()
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A Ddpu_hw_pingpong.c127 u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG); in dpu_hw_pp_get_autorefresh_config()
156 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC); in dpu_hw_pp_connect_external_te()
178 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); in dpu_hw_pp_get_vsync_info()
181 val = DPU_REG_READ(c, PP_INT_COUNT_VAL); in dpu_hw_pp_get_vsync_info()
185 val = DPU_REG_READ(c, PP_LINE_COUNT); in dpu_hw_pp_get_vsync_info()
201 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF; in dpu_hw_pp_get_line_count()
202 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; in dpu_hw_pp_get_line_count()
207 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; in dpu_hw_pp_get_line_count()
280 data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP); in dpu_hw_pp_setup_dsc()
A Ddpu_hw_ctl.c91 return DPU_REG_READ(c, CTL_FLUSH); in dpu_hw_ctl_get_flush_register()
422 status = DPU_REG_READ(c, CTL_SW_RESET); in dpu_hw_ctl_poll_reset_status()
448 status = DPU_REG_READ(c, CTL_SW_RESET); in dpu_hw_ctl_wait_reset_status()
588 intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); in dpu_hw_ctl_intf_cfg_v1()
589 wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); in dpu_hw_ctl_intf_cfg_v1()
590 cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE); in dpu_hw_ctl_intf_cfg_v1()
591 dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); in dpu_hw_ctl_intf_cfg_v1()
710 cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE); in dpu_hw_ctl_reset_intf_cfg_v1()
716 wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); in dpu_hw_ctl_reset_intf_cfg_v1()
722 dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); in dpu_hw_ctl_reset_intf_cfg_v1()
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A Ddpu_hw_top.c94 value = DPU_REG_READ(c, DANGER_STATUS); in dpu_hw_get_danger_status()
158 reg = DPU_REG_READ(c, wd_ctl2); in dpu_hw_setup_wd_timer()
180 reg = DPU_REG_READ(c, MDP_VSYNC_SEL); in dpu_hw_setup_vsync_sel()
206 value = DPU_REG_READ(c, SAFE_STATUS); in dpu_hw_get_safe_status()
A Ddpu_hw_sspp.c161 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); in dpu_hw_sspp_setup_multirect()
182 opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE); in _sspp_setup_opmode()
198 opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE); in _sspp_setup_csc10_opmode()
235 opmode = DPU_REG_READ(c, op_mode_off); in dpu_hw_sspp_setup_format()
478 ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0); in dpu_hw_sspp_setup_sourceaddress()
479 ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1); in dpu_hw_sspp_setup_sourceaddress()
A Ddpu_hw_lm.c73 op_mode = DPU_REG_READ(c, LM_OP_MODE); in dpu_hw_lm_setup_out()
193 op_mode = DPU_REG_READ(c, LM_OP_MODE); in dpu_hw_lm_setup_color3()
216 op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off); in dpu_hw_lm_setup_color3_v12()
A Ddpu_hw_interrupts.c265 irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off); in dpu_core_irq()
268 enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off); in dpu_core_irq()
475 intr_status = DPU_REG_READ(&intr->hw, in dpu_core_irq_read()
A Ddpu_hw_util.c506 ctrl = DPU_REG_READ(c, misr_ctrl_offset); in dpu_hw_collect_misr()
514 *misr_value = DPU_REG_READ(c, misr_signature_offset); in dpu_hw_collect_misr()
547 reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off); in dpu_hw_clk_force_ctrl()
A Ddpu_hw_cdm.c214 mux_cfg = DPU_REG_READ(c, CDM_MUX); in dpu_hw_cdm_bind_pingpong_blk()
A Ddpu_hw_util.h340 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) macro
A Ddpu_hw_wb.c173 mux_cfg = DPU_REG_READ(c, WB_MUX); in dpu_hw_wb_bind_pingpong_blk()

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