Searched refs:DP_DSC_CNTL (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| A D | dcn20_stream_encoder.c | 287 REG_UPDATE_2(DP_DSC_CNTL, in enc2_dp_set_dsc_config()
356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
358 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
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| A D | dcn20_stream_encoder.h | 37 SRI(DP_DSC_CNTL, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.c | 310 REG_UPDATE_2(DP_DSC_CNTL, in enc3_dp_set_dsc_config()
392 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
394 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc3_read_state()
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| A D | dcn30_dio_stream_encoder.h | 101 SRI(DP_DSC_CNTL, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.c | 399 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc314_dp_set_dsc_config()
410 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc314_read_state()
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| A D | dcn314_dio_stream_encoder.h | 100 SRI(DP_DSC_CNTL, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.c | 361 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc32_dp_set_dsc_config()
372 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc32_read_state()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 131 SRI_ARR(DP_DSC_CNTL, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.h | 98 SRI(DP_DSC_CNTL, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.h | 176 uint32_t DP_DSC_CNTL; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 300 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \
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Completed in 17 milliseconds