| /drivers/gpu/drm/i915/display/ |
| A D | intel_dp_link_training.h | 29 const u8 link_status[DP_LINK_STATUS_SIZE]); 45 const u8 link_status[DP_LINK_STATUS_SIZE]);
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| A D | intel_dp_link_training.c | 391 const u8 link_status[DP_LINK_STATUS_SIZE], in intel_dp_get_lane_adjust_tx_ffe_preset() argument 411 const u8 link_status[DP_LINK_STATUS_SIZE], in intel_dp_get_lane_adjust_vswing_preemph() argument 447 const u8 link_status[DP_LINK_STATUS_SIZE], in intel_dp_get_lane_adjust_train() argument 485 const u8 link_status[DP_LINK_STATUS_SIZE]) in intel_dp_get_adjust_train() argument 824 const u8 old_link_status[DP_LINK_STATUS_SIZE], in intel_dp_adjust_request_changed() argument 851 const u8 link_status[DP_LINK_STATUS_SIZE]) in intel_dp_dump_link_status() argument 868 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; in intel_dp_link_training_clock_recovery() 870 u8 link_status[DP_LINK_STATUS_SIZE]; in intel_dp_link_training_clock_recovery() 1021 u8 link_status[DP_LINK_STATUS_SIZE]; in intel_dp_link_training_channel_equalization() 1387 u8 link_status[DP_LINK_STATUS_SIZE]; in intel_dp_128b132b_lane_eq() [all …]
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| A D | intel_dp_test.c | 313 u8 link_status[DP_LINK_STATUS_SIZE]; in intel_dp_process_phy_request()
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| A D | intel_dp.c | 5036 u8 link_status[DP_LINK_STATUS_SIZE]) in intel_dp_link_ok() argument 5078 u8 link_status[DP_LINK_STATUS_SIZE] = {}; in intel_dp_mst_link_status() 5079 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; in intel_dp_mst_link_status() 5188 u8 link_status[DP_LINK_STATUS_SIZE]; in intel_dp_needs_link_retrain()
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| /drivers/gpu/drm/display/ |
| A D | drm_dp_helper.c | 76 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) in dp_link_status() argument 81 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], in dp_get_lane_status() argument 91 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], in drm_dp_channel_eq_ok() argument 111 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], in drm_dp_clock_recovery_ok() argument 153 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], in drm_dp_get_adjust_tx_ffe_preset() argument 801 u8 status[DP_LINK_STATUS_SIZE]) in drm_dp_dpcd_read_link_status() argument 804 DP_LINK_STATUS_SIZE); in drm_dp_dpcd_read_link_status() 823 u8 link_status[DP_LINK_STATUS_SIZE]) in drm_dp_dpcd_read_phy_link_status() argument 831 DP_LINK_STATUS_SIZE); in drm_dp_dpcd_read_phy_link_status() 836 DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status() [all …]
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| /drivers/gpu/drm/hisilicon/hibmc/dp/ |
| A D | dp_link.c | 139 u8 lane_status[DP_LINK_STATUS_SIZE]) in hibmc_dp_link_get_adjust_train() argument 200 u8 lane_status[DP_LINK_STATUS_SIZE] = {0}; in hibmc_dp_link_training_cr() 257 u8 lane_status[DP_LINK_STATUS_SIZE] = {0}; in hibmc_dp_link_training_channel_eq()
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| /drivers/gpu/drm/tegra/ |
| A D | dp.c | 481 u8 status[DP_LINK_STATUS_SIZE]) in drm_dp_link_get_adjustments() argument 530 u8 status[DP_LINK_STATUS_SIZE]; in drm_dp_link_recover_clock() 580 u8 status[DP_LINK_STATUS_SIZE]; in drm_dp_link_equalize_channel() 723 u8 status[DP_LINK_STATUS_SIZE]; in drm_dp_link_train_fast()
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| /drivers/gpu/drm/bridge/cadence/ |
| A D | cdns-mhdp8546-core.c | 496 u8 link_status[DP_LINK_STATUS_SIZE]) in cdns_mhdp_adjust_lt() argument 524 sizeof(hdr) + DP_LINK_STATUS_SIZE); in cdns_mhdp_adjust_lt() 537 DP_LINK_STATUS_SIZE); in cdns_mhdp_adjust_lt() 859 u8 link_status[DP_LINK_STATUS_SIZE], in cdns_mhdp_get_adjust_train() argument 903 void cdns_mhdp_set_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], in cdns_mhdp_set_adjust_request_voltage() argument 929 u8 link_status[DP_LINK_STATUS_SIZE]) in cdns_mhdp_adjust_requested_eq() argument 978 u8 link_status[DP_LINK_STATUS_SIZE]; in cdns_mhdp_link_training_channel_eq() 1039 u8 link_status[DP_LINK_STATUS_SIZE], in cdns_mhdp_adjust_requested_cr() argument 1063 u8 after_cr[DP_LINK_STATUS_SIZE], u8 *req_volt, in cdns_mhdp_validate_cr() argument 1103 u8 link_status[DP_LINK_STATUS_SIZE]; in cdns_mhdp_link_training_cr() [all …]
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| /drivers/gpu/drm/gma500/ |
| A D | cdv_intel_dp.c | 268 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1233 DP_LINK_STATUS_SIZE); in cdv_intel_dp_get_link_status() 1237 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], in cdv_intel_dp_link_status() argument 1244 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], in cdv_intel_get_adjust_request_voltage() argument 1257 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], in cdv_intel_get_adjust_request_pre_emphasis() argument 1301 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], in cdv_intel_get_lane_status() argument 1313 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) in cdv_intel_clock_recovery_ok() argument
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | atombios_dp.c | 203 static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], in amdgpu_atombios_dp_get_adjust_train() argument 458 u8 link_status[DP_LINK_STATUS_SIZE]; in amdgpu_atombios_dp_needs_link_train() 497 u8 link_status[DP_LINK_STATUS_SIZE];
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| /drivers/gpu/drm/radeon/ |
| A D | atombios_dp.c | 252 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], in dp_get_adjust_train() argument 501 u8 link_status[DP_LINK_STATUS_SIZE]; in radeon_dp_needs_link_train() 542 u8 link_status[DP_LINK_STATUS_SIZE];
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| /drivers/gpu/drm/nouveau/ |
| A D | nouveau_dp.c | 343 u8 stat[DP_LINK_STATUS_SIZE]; in nouveau_dp_train_link() 452 u8 link_status[DP_LINK_STATUS_SIZE]; in nouveau_dp_link_check_locked()
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| /drivers/gpu/drm/xlnx/ |
| A D | zynqmp_dp.c | 695 u8 link_status[DP_LINK_STATUS_SIZE]) in zynqmp_dp_adjust_train() argument 763 u8 link_status[DP_LINK_STATUS_SIZE]; in zynqmp_dp_link_train_cr() 829 u8 link_status[DP_LINK_STATUS_SIZE]; in zynqmp_dp_link_train_ce() 2338 u8 status[DP_LINK_STATUS_SIZE + 2]; in zynqmp_dp_hpd_irq_work_func() 2346 DP_LINK_STATUS_SIZE + 2); in zynqmp_dp_hpd_irq_work_func()
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| /drivers/gpu/drm/msm/dp/ |
| A D | dp_ctrl.c | 1418 u8 link_status[DP_LINK_STATUS_SIZE]; in msm_dp_ctrl_link_train_1() 1537 u8 link_status[DP_LINK_STATUS_SIZE]; in msm_dp_ctrl_link_train_2() 2233 const u8 link_status[DP_LINK_STATUS_SIZE], in msm_dp_ctrl_clock_recovery_any_ok() argument 2253 u8 link_status[DP_LINK_STATUS_SIZE]; in msm_dp_ctrl_channel_eq_ok() 2268 u8 link_status[DP_LINK_STATUS_SIZE]; in msm_dp_ctrl_on_link()
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| A D | dp_link.c | 46 u8 link_status[DP_LINK_STATUS_SIZE]; 939 static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) in get_link_status() argument
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| /drivers/gpu/drm/rockchip/ |
| A D | cdn-dp-core.c | 530 u8 link_status[DP_LINK_STATUS_SIZE]; in cdn_dp_check_link_status() 538 DP_LINK_STATUS_SIZE)) { in cdn_dp_check_link_status()
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| /drivers/gpu/drm/bridge/ |
| A D | ite-it6505.c | 1877 u8 link_status[DP_LINK_STATUS_SIZE] = { 0 }; in it6505_step_cr_train() 1950 u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 }; in it6505_step_eq_train() 2279 u8 link_status[DP_LINK_STATUS_SIZE] = { 0 }; in it6505_hdcp_work() 2460 u8 link_status[DP_LINK_STATUS_SIZE]; in it6505_process_hpd_irq()
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| A D | tc358767.c | 1094 u8 tmp[DP_LINK_STATUS_SIZE]; in tc_main_link_enable()
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| /drivers/gpu/drm/mediatek/ |
| A D | mtk_dp.c | 1626 u8 link_status[DP_LINK_STATUS_SIZE] = {}; in mtk_dp_train_cr() 1697 u8 link_status[DP_LINK_STATUS_SIZE] = {}; in mtk_dp_train_eq()
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