| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.c | 298 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, in dce110_stream_encoder_dp_set_stream_attribute()
302 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, in dce110_stream_encoder_dp_set_stream_attribute()
310 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, in dce110_stream_encoder_dp_set_stream_attribute()
318 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, in dce110_stream_encoder_dp_set_stream_attribute()
327 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, in dce110_stream_encoder_dp_set_stream_attribute()
339 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, in dce110_stream_encoder_dp_set_stream_attribute()
343 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, in dce110_stream_encoder_dp_set_stream_attribute()
347 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, in dce110_stream_encoder_dp_set_stream_attribute()
352 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, in dce110_stream_encoder_dp_set_stream_attribute()
356 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, in dce110_stream_encoder_dp_set_stream_attribute()
[all …]
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| A D | dce_stream_encoder.h | 86 SRI(DP_PIXEL_FORMAT, DP, id), \
132 SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
133 SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
134 SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
135 SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
658 uint32_t DP_PIXEL_FORMAT; member
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| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.c | 101 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine); in enc314_dp_set_odm_combine()
344 REG_UPDATE(DP_PIXEL_FORMAT, in enc314_stream_encoder_dp_unblank()
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| A D | dcn314_dio_stream_encoder.h | 87 SRI(DP_PIXEL_FORMAT, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.c | 59 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, two_pixel_per_cyle ? 1 : 0); in enc32_dp_set_odm_combine()
292 REG_UPDATE(DP_PIXEL_FORMAT, in enc32_stream_encoder_dp_unblank()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.c | 384 REG_GET(DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, &s->dsc_mode); in enc401_read_state()
579 REG_UPDATE_4(DP_PIXEL_FORMAT, in enc401_stream_encoder_dp_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.c | 324 REG_UPDATE(DP_PIXEL_FORMAT, in enc35_stream_encoder_dp_unblank()
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| A D | dcn35_dio_stream_encoder.h | 85 SRI(DP_PIXEL_FORMAT, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 340 REG_UPDATE_2(DP_PIXEL_FORMAT, in enc1_stream_encoder_dp_set_stream_attribute()
1523 REG_GET_2(DP_PIXEL_FORMAT, in enc1_stream_encoder_dp_get_pixel_format()
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| A D | dcn10_stream_encoder.h | 84 SRI(DP_PIXEL_FORMAT, DP, id), \
133 uint32_t DP_PIXEL_FORMAT; member
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| /drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| A D | dcn20_stream_encoder.c | 559 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); in enc2_dp_set_odm_combine()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 118 SRI_ARR(DP_PIXEL_FORMAT, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.h | 86 SRI(DP_PIXEL_FORMAT, DP, id), \
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| A D | dcn30_dio_stream_encoder.c | 524 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); in enc3_dp_set_odm_combine()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 205 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 294 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
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