Searched refs:DP_SEC_CNTL2 (Results 1 – 10 of 10) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 795 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
799 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); in enc1_stream_encoder_send_immediate_sdp_message()
802 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); in enc1_stream_encoder_send_immediate_sdp_message()
861 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); in enc1_stream_encoder_send_immediate_sdp_message()
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| A D | dcn10_stream_encoder.h | 87 SRI(DP_SEC_CNTL2, DP, id), \
136 uint32_t DP_SEC_CNTL2; member
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| /drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| A D | dcn20_stream_encoder.c | 228 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1); in enc2_update_gsp7_128_info_packet()
343 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0); in enc2_dp_set_dsc_pps_info_packet()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.c | 331 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1); in enc3_dp_set_dsc_pps_info_packet()
379 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0); in enc3_dp_set_dsc_pps_info_packet()
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| A D | dcn30_dio_stream_encoder.h | 89 SRI(DP_SEC_CNTL2, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 121 SRI_ARR(DP_SEC_CNTL2, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.h | 90 SRI(DP_SEC_CNTL2, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.h | 88 SRI(DP_SEC_CNTL2, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 206 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 295 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
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Completed in 19 milliseconds