Searched refs:DP_SEC_GSP0_ENABLE (Results 1 – 10 of 10) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.h | 155 SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
236 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
425 uint8_t DP_SEC_GSP0_ENABLE; member
557 uint32_t DP_SEC_GSP0_ENABLE; member
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| A D | dce_stream_encoder.c | 857 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in dce110_stream_encoder_update_dp_info_packets()
882 DP_SEC_GSP0_ENABLE, 0, in dce110_stream_encoder_stop_dp_info_packets()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.h | 54 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.h | 55 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 764 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in enc1_stream_encoder_update_dp_info_packets()
883 DP_SEC_GSP0_ENABLE, 0, in enc1_stream_encoder_stop_dp_info_packets()
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| A D | dcn10_stream_encoder.h | 224 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
432 type DP_SEC_GSP0_ENABLE;\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.h | 133 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.h | 134 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.h | 134 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| A D | dcn30_dio_stream_encoder.c | 494 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in enc3_stream_encoder_update_dp_info_packets()
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