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Searched refs:DP_SEC_GSP2_ENABLE (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_stream_encoder.h158 SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
239 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
428 uint8_t DP_SEC_GSP2_ENABLE; member
560 uint32_t DP_SEC_GSP2_ENABLE; member
A Ddce_stream_encoder.c858 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in dce110_stream_encoder_update_dp_info_packets()
884 DP_SEC_GSP2_ENABLE, 0, in dce110_stream_encoder_stop_dp_info_packets()
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.h57 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.h58 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_stream_encoder.c765 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in enc1_stream_encoder_update_dp_info_packets()
885 DP_SEC_GSP2_ENABLE, 0, in enc1_stream_encoder_stop_dp_info_packets()
A Ddcn10_stream_encoder.h227 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
435 type DP_SEC_GSP2_ENABLE;\
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.h136 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.h137 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.h137 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
A Ddcn30_dio_stream_encoder.c495 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in enc3_stream_encoder_update_dp_info_packets()

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