Searched refs:DP_SEC_GSP3_ENABLE (Results 1 – 10 of 10) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.h | 159 SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
240 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
429 uint8_t DP_SEC_GSP3_ENABLE; member
561 uint32_t DP_SEC_GSP3_ENABLE; member
|
| A D | dce_stream_encoder.c | 859 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); in dce110_stream_encoder_update_dp_info_packets()
885 DP_SEC_GSP3_ENABLE, 0, in dce110_stream_encoder_stop_dp_info_packets()
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.h | 58 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.h | 59 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 766 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); in enc1_stream_encoder_update_dp_info_packets()
886 DP_SEC_GSP3_ENABLE, 0, in enc1_stream_encoder_stop_dp_info_packets()
|
| A D | dcn10_stream_encoder.h | 228 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
436 type DP_SEC_GSP3_ENABLE;\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.h | 137 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.h | 138 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.h | 138 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
|
| A D | dcn30_dio_stream_encoder.c | 496 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); in enc3_stream_encoder_update_dp_info_packets()
|
Completed in 18 milliseconds