Searched refs:DP_SEC_GSP5_ENABLE (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.h | 349 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
431 uint8_t DP_SEC_GSP5_ENABLE; member
563 uint32_t DP_SEC_GSP5_ENABLE; member
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.h | 96 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.h | 98 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 767 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid); in enc1_stream_encoder_update_dp_info_packets()
888 DP_SEC_GSP5_ENABLE, 0, in enc1_stream_encoder_stop_dp_info_packets()
|
| A D | dcn10_stream_encoder.h | 322 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
438 type DP_SEC_GSP5_ENABLE;\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.h | 175 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.h | 176 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.h | 188 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
|
| A D | dcn30_dio_stream_encoder.c | 497 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid); in enc3_stream_encoder_update_dp_info_packets()
|
Completed in 37 milliseconds