Searched refs:DP_STEER_FIFO_RESET (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.c | 358 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); in enc314_stream_encoder_dp_unblank()
361 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in enc314_stream_encoder_dp_unblank()
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| A D | dcn314_dio_stream_encoder.h | 148 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.c | 338 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); in enc35_stream_encoder_dp_unblank()
341 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in enc35_stream_encoder_dp_unblank()
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| A D | dcn35_dio_stream_encoder.h | 149 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
| A D | dcn32_dio_stream_encoder.c | 306 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); in enc32_stream_encoder_dp_unblank()
309 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in enc32_stream_encoder_dp_unblank()
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| A D | dcn32_dio_stream_encoder.h | 69 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.h | 165 SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
245 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
439 uint8_t DP_STEER_FIFO_RESET; member
571 uint32_t DP_STEER_FIFO_RESET; member
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| A D | dce_stream_encoder.c | 945 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); in dce110_stream_encoder_dp_blank()
994 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in dce110_stream_encoder_dp_unblank()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| A D | dcn20_stream_encoder.c | 529 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); in enc2_stream_encoder_dp_unblank()
532 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in enc2_stream_encoder_dp_unblank()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.c | 331 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); in enc401_stream_encoder_dp_unblank()
334 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in enc401_stream_encoder_dp_unblank()
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| A D | dcn401_dio_stream_encoder.h | 70 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 952 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); in enc1_stream_encoder_dp_blank()
1010 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); in enc1_stream_encoder_dp_unblank()
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| A D | dcn10_stream_encoder.h | 237 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
453 type DP_STEER_FIFO_RESET;\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.h | 147 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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