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Searched refs:DP_VID_STREAM_ENABLE (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.c323 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc401_stream_encoder_dp_unblank()
338 REG_UPDATE_2(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 1, DP_VID_STREAM_DIS_DEFER, 2); in enc401_stream_encoder_dp_unblank()
371 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc401_stream_encoder_dp_unblank()
A Ddcn401_dio_link_encoder.h70 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
A Ddcn401_dio_stream_encoder.h68 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c350 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc314_stream_encoder_dp_unblank()
376 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc314_stream_encoder_dp_unblank()
A Ddcn314_dio_stream_encoder.h146 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c330 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc35_stream_encoder_dp_unblank()
356 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc35_stream_encoder_dp_unblank()
A Ddcn35_dio_link_encoder.h71 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
A Ddcn35_dio_stream_encoder.h147 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c298 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc32_stream_encoder_dp_unblank()
344 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc32_stream_encoder_dp_unblank()
A Ddcn32_dio_stream_encoder.h67 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_stream_encoder.h163 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
243 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
437 uint8_t DP_VID_STREAM_ENABLE; member
569 uint32_t DP_VID_STREAM_ENABLE; member
A Ddce_stream_encoder.c914 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in dce110_stream_encoder_dp_blank()
928 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce110_stream_encoder_dp_blank()
1009 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in dce110_stream_encoder_dp_unblank()
A Ddce_link_encoder.c457 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
509 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_stream_encoder.c515 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc2_stream_encoder_dp_unblank()
547 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc2_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_stream_encoder.c918 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in enc1_stream_encoder_dp_blank()
933 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in enc1_stream_encoder_dp_blank()
1025 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc1_stream_encoder_dp_unblank()
A Ddcn10_link_encoder.h209 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
259 type DP_VID_STREAM_ENABLE;\
A Ddcn10_stream_encoder.h235 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
451 type DP_VID_STREAM_ENABLE;\
A Ddcn10_link_encoder.c389 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.h145 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\

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