Searched refs:DSCC_PPS_CONFIG1 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 101 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc401_read_state()
103 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc401_read_state()
255 REG_SET_7(DSCC_PPS_CONFIG1, 0, in dsc_write_to_registers()
|
| A D | dcn401_dsc.h | 213 uint32_t DSCC_PPS_CONFIG1; member
|
| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.c | 148 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc2_read_state()
150 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc2_read_state()
633 REG_SET_7(DSCC_PPS_CONFIG1, 0, in dsc_write_to_registers()
|
| A D | dcn20_dsc.h | 42 SRI(DSCC_PPS_CONFIG1, DSCC, id),\
475 uint32_t DSCC_PPS_CONFIG1; member
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 426 SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 731 SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \
|
Completed in 12 milliseconds