Searched refs:DSCC_PPS_CONFIG2 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 104 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc401_read_state()
105 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc401_read_state()
264 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
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| A D | dcn401_dsc.h | 214 uint32_t DSCC_PPS_CONFIG2; member
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.c | 151 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc2_read_state()
152 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc2_read_state()
642 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
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| A D | dcn20_dsc.h | 43 SRI(DSCC_PPS_CONFIG2, DSCC, id),\
476 uint32_t DSCC_PPS_CONFIG2; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 427 SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 732 SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \
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