Searched refs:DSCC_PPS_CONFIG3 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 100 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc401_read_state()
102 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc401_read_state()
268 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
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| A D | dcn401_dsc.h | 215 uint32_t DSCC_PPS_CONFIG3; member
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.c | 147 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc2_read_state()
149 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc2_read_state()
646 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
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| A D | dcn20_dsc.h | 44 SRI(DSCC_PPS_CONFIG3, DSCC, id),\
477 uint32_t DSCC_PPS_CONFIG3; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 428 SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 733 SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \
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