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Searched refs:DSCEnabled (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.c70 in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; in map_hw_resources()
139 p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1; in optimize_configuration()
A Ddisplay_mode_core_structs.h659 …dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode… member
795 …dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; us… member
A Ddisplay_mode_util.c615 dml_print("DML: hw_resource: plane=%d, DSCEnabled = %d\n", i, hw->DSCEnabled[i]); in dml_print_dml_display_cfg_hw_resource()
A Ddisplay_mode_core.c735 dml_bool_t DSCEnabled,
5871 dml_bool_t DSCEnabled, in DSCDelayRequirement() argument
5885 if (DSCEnabled == true && OutputBpp != 0) { in DSCDelayRequirement()
5903 dml_print("DML::%s: DSCEnabled = %u\n", __func__, DSCEnabled); in DSCDelayRequirement()
8251 mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k]; in dml_core_mode_support()
8584 …display_cfg.plane.BlendingAndTiming[k] != k) || !mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k]) { in dml_core_mode_programming()
8606 locals->DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k], in dml_core_mode_programming()
8621 …che_display_cfg.plane.BlendingAndTiming[k] == j && mode_lib->ms.cache_display_cfg.hw.DSCEnabled[j]) in dml_core_mode_programming()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_types.h350 …bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mod… member
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_util_32.h320 unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
A Ddisplay_mode_vba_32.c336 if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
364 v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
375 if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3748 mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k]; in dml32_ModeSupportAndSystemConfigurationFull()
A Ddisplay_mode_vba_util_32.c1717 unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, in dml32_DSCDelayRequirement() argument
1732 if (DSCEnabled == true && OutputBpp != 0) { in dml32_DSCDelayRequirement()
1757 dml_print("DML::%s: DSCEnabled = %d\n", __func__, DSCEnabled); in dml32_DSCDelayRequirement()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20v2.c1810 if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1841 if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1881 && mode_lib->vba.DSCEnabled[j]) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3264 bool DSCEnabled, in TruncToValidBPP() argument
3301 if (DSCEnabled) { in TruncToValidBPP()
4014 } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4202 if (mode_lib->vba.DSCEnabled[k] == true) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4233 if (mode_lib->vba.DSCEnabled[k] == true) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4266 if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { in dml20v2_ModeSupportAndSystemConfigurationFull()
5226 mode_lib->vba.DSCEnabled[k] = in dml20v2_ModeSupportAndSystemConfigurationFull()
A Ddisplay_mode_vba_20.c1774 if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1805 if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1845 && mode_lib->vba.DSCEnabled[j]) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3190 bool DSCEnabled, in TruncToValidBPP() argument
3227 if (DSCEnabled) { in TruncToValidBPP()
4085 if (mode_lib->vba.DSCEnabled[k] == true) { in dml20_ModeSupportAndSystemConfigurationFull()
4114 if (mode_lib->vba.DSCEnabled[k] == true) { in dml20_ModeSupportAndSystemConfigurationFull()
4145 if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { in dml20_ModeSupportAndSystemConfigurationFull()
5110 mode_lib->vba.DSCEnabled[k] = in dml20_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c1766 if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1797 if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1837 && mode_lib->vba.DSCEnabled[j]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3270 bool DSCEnabled, in TruncToValidBPP() argument
3307 if (DSCEnabled) { in TruncToValidBPP()
4108 } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) { in dml21_ModeSupportAndSystemConfigurationFull()
4296 if (mode_lib->vba.DSCEnabled[k] == true) { in dml21_ModeSupportAndSystemConfigurationFull()
4327 if (mode_lib->vba.DSCEnabled[k] == true) { in dml21_ModeSupportAndSystemConfigurationFull()
4360 if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { in dml21_ModeSupportAndSystemConfigurationFull()
5232 mode_lib->vba.DSCEnabled[k] = in dml21_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.h508 bool DSCEnabled[DC__NUM_DPP__MAX]; member
A Ddisplay_mode_vba.c647 mode_lib->vba.DSCEnabled[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable; in fetch_pipe_params()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4.c517 …pport_info[stream_index].dsc_enable = l->mode_support_ex_params.out_evaluation_info->DSCEnabled[i]; in core_dcn4_mode_support()
A Ddml2_core_shared_types.h280 …bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mod… member
A Ddml2_core_dcn4_calcs.c4476 bool DSCEnabled, in DSCDelayRequirement() argument
4491 if (DSCEnabled == true && OutputBpp != 0) { in DSCDelayRequirement()
4510 DML_LOG_VERBOSE("DML::%s: DSCEnabled= %u\n", __func__, DSCEnabled); in DSCDelayRequirement()
9558 mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k]; in dml_core_mode_support()
9566 …DML_LOG_VERBOSE("DML::%s: k=%d, DSCEnabled = %u\n", __func__, k, mode_lib->ms.support.DSCEnabled[k… in dml_core_mode_support()
13028 out->informative.mode_support_info.DSCEnabled[k] = mode_lib->ms.support.DSCEnabled[k]; in dml2_core_calcs_get_informative()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c2097 if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2124 if (v->DSCEnabled[k] && BPP != 0) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2159 && v->DSCEnabled[j]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3890 if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH in dml30_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c2227 if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
2254 if (v->DSCEnabled[k] && BPP != 0) {
2290 if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
4114 if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c2245 if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
2272 if (v->DSCEnabled[k] && BPP != 0) {
2309 if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
4204 if (v->DSCEnabled[k] && v->HActive[k] > DCN314_MAX_DSC_IMAGE_WIDTH

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