Searched refs:DSPFW1 (Results 1 – 8 of 8) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| A D | psb_device.c | 114 regs->saveDSPFW1 = PSB_RVDC32(DSPFW1); in psb_save_display_registers()
158 PSB_WVDC32(regs->saveDSPFW1, DSPFW1); in psb_restore_display_registers()
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| A D | cdv_intel_display.c | 500 fw = REG_READ(DSPFW1); in cdv_update_wm()
505 REG_WRITE(DSPFW1, fw); in cdv_update_wm()
542 REG_WRITE(DSPFW1, 0x3f880808); in cdv_update_wm()
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| A D | oaktrail_device.c | 131 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1); in oaktrail_save_display_registers()
245 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1); in oaktrail_restore_display_registers()
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| A D | cdv_device.c | 244 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); in cdv_save_display_registers()
318 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
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| A D | oaktrail_crtc.c | 332 REG_WRITE(DSPFW1, 0x3f8f0404); in oaktrail_crtc_dpms()
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| A D | psb_intel_reg.h | 570 #define DSPFW1 0x70034 macro
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| /drivers/gpu/drm/i915/display/ |
| A D | i9xx_wm_regs.h | 44 #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) macro
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| A D | i9xx_wm.c | 670 reg = intel_de_read(display, DSPFW1(display)); in pnv_update_wm()
673 intel_de_write(display, DSPFW1(display), reg); in pnv_update_wm()
804 intel_de_write(display, DSPFW1(display), in g4x_write_wm_values()
822 intel_de_posting_read(display, DSPFW1(display)); in g4x_write_wm_values()
854 intel_de_write(display, DSPFW1(display), in vlv_write_wm_values()
901 intel_de_posting_read(display, DSPFW1(display)); in vlv_write_wm_values()
2184 intel_de_write(display, DSPFW1(display), in i965_update_wm()
3661 tmp = intel_de_read(display, DSPFW1(display)); in g4x_read_wm_values()
3701 tmp = intel_de_read(display, DSPFW1(display)); in vlv_read_wm_values()
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