Searched refs:DSPFW3 (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| A D | psb_device.c | 116 regs->saveDSPFW3 = PSB_RVDC32(DSPFW3); in psb_save_display_registers()
160 PSB_WVDC32(regs->saveDSPFW3, DSPFW3); in psb_restore_display_registers()
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| A D | oaktrail_device.c | 133 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); in oaktrail_save_display_registers()
247 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3); in oaktrail_restore_display_registers()
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| A D | cdv_device.c | 246 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); in cdv_save_display_registers()
320 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); in cdv_restore_display_registers()
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| A D | cdv_intel_display.c | 514 REG_WRITE(DSPFW3, 0x36000000); in cdv_update_wm()
544 REG_WRITE(DSPFW3, 0x24000000); in cdv_update_wm()
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| A D | oaktrail_crtc.c | 334 REG_WRITE(DSPFW3, 0x0); in oaktrail_crtc_dpms()
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| A D | psb_intel_reg.h | 580 #define DSPFW3 0x7003c macro
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| /drivers/gpu/drm/i915/display/ |
| A D | i9xx_wm_regs.h | 71 #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) macro
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| A D | i9xx_wm.c | 165 val = intel_de_read(display, DSPFW3(display)); in _intel_set_memory_cxsr()
171 intel_de_write(display, DSPFW3(display), val); in _intel_set_memory_cxsr()
172 intel_de_posting_read(display, DSPFW3(display)); in _intel_set_memory_cxsr()
681 intel_de_rmw(display, DSPFW3(display), in pnv_update_wm()
689 intel_de_rmw(display, DSPFW3(display), in pnv_update_wm()
697 reg = intel_de_read(display, DSPFW3(display)); in pnv_update_wm()
700 intel_de_write(display, DSPFW3(display), reg); in pnv_update_wm()
816 intel_de_write(display, DSPFW3(display), in g4x_write_wm_values()
863 intel_de_write(display, DSPFW3(display), in vlv_write_wm_values()
2193 intel_de_write(display, DSPFW3(display), in i965_update_wm()
[all …]
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| A D | intel_display_debugfs.c | 105 sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN; in i915_sr_status()
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