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Searched refs:DSPP_0 (Results 1 – 25 of 37) sorted by relevance

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/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_6_5_qcm2290.h62 .dspp = DSPP_0,
68 .name = "dspp_0", .id = DSPP_0,
A Ddpu_6_3_sm6115.h62 .dspp = DSPP_0,
68 .name = "dspp_0", .id = DSPP_0,
A Ddpu_6_9_sm6375.h64 .dspp = DSPP_0,
70 .name = "dspp_0", .id = DSPP_0,
A Ddpu_4_1_sdm670.h75 .dspp = DSPP_0,
103 .name = "dspp_0", .id = DSPP_0,
A Ddpu_1_15_msm8917.h87 .dspp = DSPP_0,
103 .name = "dspp_0", .id = DSPP_0,
A Ddpu_1_14_msm8937.h88 .dspp = DSPP_0,
116 .name = "dspp_0", .id = DSPP_0,
A Ddpu_1_16_msm8953.h88 .dspp = DSPP_0,
116 .name = "dspp_0", .id = DSPP_0,
A Ddpu_5_4_sm6125.h95 .dspp = DSPP_0,
109 .name = "dspp_0", .id = DSPP_0,
A Ddpu_6_2_sc7180.h91 .dspp = DSPP_0,
104 .name = "dspp_0", .id = DSPP_0,
A Ddpu_3_3_sdm630.h103 .dspp = DSPP_0,
131 .name = "dspp_0", .id = DSPP_0,
A Ddpu_6_4_sm6350.h98 .dspp = DSPP_0,
112 .name = "dspp_0", .id = DSPP_0,
A Ddpu_5_3_sm6150.h111 .dspp = DSPP_0,
127 .name = "dspp_0", .id = DSPP_0,
A Ddpu_7_2_sc7280.h94 .dspp = DSPP_0,
114 .name = "dspp_0", .id = DSPP_0,
A Ddpu_3_2_sdm660.h113 .dspp = DSPP_0,
179 .name = "dspp_0", .id = DSPP_0,
A Ddpu_1_7_msm8996.h153 .dspp = DSPP_0,
219 .name = "dspp_0", .id = DSPP_0,
A Ddpu_3_0_msm8998.h142 .dspp = DSPP_0,
208 .name = "dspp_0", .id = DSPP_0,
A Ddpu_5_2_sm7150.h116 .dspp = DSPP_0,
144 .name = "dspp_0", .id = DSPP_0,
A Ddpu_4_0_sdm845.h140 .dspp = DSPP_0,
170 .name = "dspp_0", .id = DSPP_0,
A Ddpu_5_0_sm8150.h143 .dspp = DSPP_0,
187 .name = "dspp_0", .id = DSPP_0,
A Ddpu_6_0_sm8250.h142 .dspp = DSPP_0,
186 .name = "dspp_0", .id = DSPP_0,
A Ddpu_7_0_sm8350.h142 .dspp = DSPP_0,
186 .name = "dspp_0", .id = DSPP_0,
A Ddpu_9_0_sm8550.h139 .dspp = DSPP_0,
183 .name = "dspp_0", .id = DSPP_0,
A Ddpu_9_1_sar2130p.h139 .dspp = DSPP_0,
183 .name = "dspp_0", .id = DSPP_0,
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_ctl.c160 for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { in dpu_hw_ctl_trigger_flush_v1()
161 if (ctx->pending_dspp_flush_mask[dspp - DSPP_0]) in dpu_hw_ctl_trigger_flush_v1()
163 CTL_DSPP_n_FLUSH(dspp - DSPP_0), in dpu_hw_ctl_trigger_flush_v1()
164 ctx->pending_dspp_flush_mask[dspp - DSPP_0]); in dpu_hw_ctl_trigger_flush_v1()
375 case DSPP_0: in dpu_hw_ctl_update_pending_flush_dspp()
400 ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); in dpu_hw_ctl_update_pending_flush_dspp_sub_blocks()
A Ddpu_rm.h36 struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];

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