Searched refs:EDP_PSR_STATUS_STATE_MASK (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_psr_regs.h | 106 #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29) macro
107 #define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)
108 #define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)
109 #define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2)
110 #define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3)
111 #define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4)
112 #define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5)
113 #define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6)
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| A D | intel_psr.c | 2134 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; in intel_psr_wait_exit_locked()
3034 EDP_PSR_STATUS_STATE_MASK, 50); in _psr1_ready_for_pipe_update_locked()
3090 mask = EDP_PSR_STATUS_STATE_MASK; in __psr_wait_for_idle_locked()
3923 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); in psr_source_status()
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