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Searched refs:EMC_TIMING_CONTROL (Results 1 – 5 of 5) sorted by relevance

/drivers/memory/tegra/
A Dtegra20-emc.c40 #define EMC_TIMING_CONTROL 0x028 macro
309 emc->regs + EMC_TIMING_CONTROL); in emc_complete_timing_change()
A Dtegra124-emc.c51 #define EMC_TIMING_CONTROL 0x28 macro
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
A Dtegra30-emc.c46 #define EMC_TIMING_CONTROL 0x028 macro
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
A Dtegra210-emc.h35 #define EMC_TIMING_CONTROL 0x28 macro
A Dtegra210-emc-core.c908 emc_writel(emc, 0x1, EMC_TIMING_CONTROL); in tegra210_emc_timing_update()
1155 emc_writel(emc, 1, EMC_TIMING_CONTROL); in tegra210_emc_dll_prelock()

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