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Searched refs:ENABLE (Results 1 – 25 of 97) sorted by relevance

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/drivers/gpu/drm/nouveau/dispnv50/
A Dwndwca7e.c29 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, DISABLE)); in wndwca7e_image_clr()
57 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, ENABLE)); in wndwca7e_image_set()
107 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, DISABLE)); in wndwca7e_ilut_clr()
129 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, ENABLE)); in wndwca7e_ilut_set()
150 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, DISABLE)); in wndwca7e_ntfy_clr()
174 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE)); in wndwca7e_ntfy_set()
A Dheadca7d.c101 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in headca7d_dither()
122 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | in headca7d_curs_clr()
126 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, DISABLE)); in headca7d_curs_clr()
149 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, ENABLE)); in headca7d_curs_set()
152 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | in headca7d_curs_set()
181 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, DISABLE)); in headca7d_olut_clr()
204 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, ENABLE)); in headca7d_olut_set()
A Dhead827d.c40 NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | in head827d_curs_clr()
59 NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | in head827d_curs_set()
121 NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE)); in head827d_olut_clr()
138 NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) | in head827d_olut_set()
A Dcrcca7d.c33 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, ENABLE)); in crcca7d_set_ctx()
36 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, DISABLE)); in crcca7d_set_ctx()
A Dbase907c.c75 NVDEF(NV907C, SET_BASE_LUT_LO, ENABLE, DISABLE)); in base907c_xlut_clr()
78 NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, DISABLE)); in base907c_xlut_clr()
94 NVVAL(NV907C, SET_BASE_LUT_LO, ENABLE, asyw->xlut.i.enable) | in base907c_xlut_set()
100 NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, USE_CORE_LUT)); in base907c_xlut_set()
A Dcoreca7d.c34 NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE)); in coreca7d_update()
38 NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE)); in coreca7d_update()
A Dhead917d.c41 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head917d_dither()
89 NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | in head917d_curs_set()
A Dhead507d.c59 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head507d_dither()
133 NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | in head507d_curs_clr()
150 NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | in head507d_curs_set()
289 NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE)); in head507d_olut_clr()
304 NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) | in head507d_olut_set()
A Dhead907d.c88 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head907d_dither()
163 NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | in head907d_curs_clr()
182 NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | in head907d_curs_set()
257 NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, DISABLE)); in head907d_olut_clr()
274 NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) | in head907d_olut_set()
A Dheadc37d.c96 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in headc37d_dither()
115 NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | in headc37d_curs_clr()
133 NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | in headc37d_curs_set()
A Dcore507d.c46 NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE)); in core507d_update()
93 NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE)); in core507d_read_caps()
A Dbase507c.c82 NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, ENABLE), in base507c_image_set()
128 NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, DISABLE)); in base507c_xlut_clr()
142 NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, USE_CORE_LUT)); in base507c_xlut_set()
/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
A Ddcn32_dccg.h80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
/drivers/gpu/drm/nouveau/
A Dnouveau_connector.h71 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, DISABLE),
73 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, ENABLE),
/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
A Ddcn31_dccg.h113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
115 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
116 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.h111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
/drivers/gpu/drm/amd/amdgpu/
A Dvega20_ih.c227 ENABLE, 1); in vega20_ih_doorbell_rptr()
231 ENABLE, 0); in vega20_ih_doorbell_rptr()
291 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); in vega20_setup_retry_doorbell()
373 ENABLE, 1); in vega20_ih_irq_init()
375 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); in vega20_ih_irq_init()
/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.h108 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\
109 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\
110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\
/drivers/net/ethernet/freescale/dpaa2/
A Ddpni.c268 *en = dpni_get_field(rsp_params->enabled, ENABLE); in dpni_is_enabled()
325 dpni_set_field(cmd_params->enable, ENABLE, en); in dpni_set_irq_enable()
368 *en = dpni_get_field(rsp_params->enabled, ENABLE); in dpni_get_irq_enable()
1024 dpni_set_field(cmd_params->enable, ENABLE, en); in dpni_set_multicast_promisc()
1060 *en = dpni_get_field(rsp_params->enabled, ENABLE); in dpni_get_multicast_promisc()
1087 dpni_set_field(cmd_params->enable, ENABLE, en); in dpni_set_unicast_promisc()
1123 *en = dpni_get_field(rsp_params->enabled, ENABLE); in dpni_get_unicast_promisc()
1255 dpni_set_field(cmd_params->en, ENABLE, en); in dpni_enable_vlan_filter()
1691 dpni_set_field(cmd_params->enable, ENABLE, taildrop->enable); in dpni_set_taildrop()
1745 taildrop->enable = dpni_get_field(rsp_params->enable, ENABLE); in dpni_get_taildrop()
/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
A Ddcn35_dccg.h102 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
103 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
104 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
105 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
/drivers/net/wireless/ti/wl1251/
A Dreg.h48 #define ENABLE (REGISTERS_BASE + 0x5450) macro
277 #define REG_ENABLE_TX_RX (ENABLE)
/drivers/net/plip/
A Dplip.c125 #define ENABLE(irq) if (irq != -1) enable_irq(irq) macro
616 ENABLE(dev->irq); in plip_receive_packet()
694 ENABLE(dev->irq); in plip_receive_packet()
700 ENABLE(dev->irq); in plip_receive_packet()
800 ENABLE(dev->irq); in plip_send_packet()
869 ENABLE(dev->irq); in plip_send_packet()
907 ENABLE(dev->irq); in plip_error()
/drivers/char/
A Ddsp56k.c60 #define handshake(count, maxio, timeout, ENABLE, f) \ argument
66 for (t = 0; t < timeout && !ENABLE; t++) \
68 if(!ENABLE) \
/drivers/scsi/aic7xxx/
A Daic7770.c236 ahc_outb(ahc, BCTL, ENABLE); in aic7770_config()
246 ahc_outb(ahc, BCTL, ENABLE); in aic7770_chip_init()
/drivers/media/pci/cobalt/
A Dcobalt-omnitek.c26 #define ENABLE (1 << 0) macro
102 iowrite32(ENABLE | SCATTER_GATHER_MODE | START, CS_REG(s->dma_channel)); in omni_sg_dma_start()

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