Searched refs:EP (Results 1 – 9 of 9) sorted by relevance
523 #define ep_index(EP) ((EP)->ep.desc->bEndpointAddress&0xF) argument524 #define ep_maxpacket(EP) ((EP)->ep.maxpacket) argument525 #define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ argument526 USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \532 #define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) argument
152 #define ep_index(EP) ((EP)->ep.desc->bEndpointAddress & 0xF) argument153 #define ep_maxpacket(EP) ((EP)->ep.maxpacket) argument154 #define ep_is_in(EP) ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ argument155 USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \
35 This enables the EP's MSI interrupt controller to function as a36 doorbell. The RC can trigger doorbell in EP by writing data to a37 dedicated BAR, which the EP maps to the controller's message address.
131 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]132 determines which PCIe controller works in EP mode and which PCIe143 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]144 determines which PCIe controller works in EP mode and which PCIe238 Tegra194. This controller can work either as EP or RC. In order to253 Tegra194. This controller can work either as EP or RC. In order to270 This controller can work either as EP or RC. In order to enable285 This controller can work either as EP or RC. In order to enable439 This controller can work either as EP or RC. In order to enable454 This controller can work either as EP or RC. In order to enable
99 #define EP 0x0 macro1088 val = EP; in ks_pcie_am654_set_mode()
47 tristate "DataStor EP-2000 protocol"50 This option enables support for the EP-2000 parallel port IDE
56 Surecom EP-9428
96 EP = 0, enumerator
69 AIR0501 "AIR 586EP PCI/EISA System Board"
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