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Searched refs:FIELD_SET (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/xe/
A Dxe_tuning.c34 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
39 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
72 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
77 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
113 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
132 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
140 XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
A Dxe_hw_engine.c387 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0), in xe_hw_engine_setup_default_lrc_state()
396 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0), in xe_hw_engine_setup_default_lrc_state()
431 XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), in hw_engine_setup_default_state()
448 FIELD_SET(RING_PWRCTX_MAXCNT(0), in hw_engine_setup_default_state()
462 XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, in hw_engine_setup_default_state()
A Dxe_wa.c392 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
641 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
688 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
723 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
/drivers/soc/qcom/
A Dspm.c26 #define FIELD_SET(current, mask, val) \ macro
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
357 data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel); in smp_set_vdd_v1_1()
358 data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel); in smp_set_vdd_v1_1()
376 avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); in smp_set_vdd_v1_1()
377 avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); in smp_set_vdd_v1_1()
/drivers/net/ethernet/marvell/octeontx2/af/
A Dcgx.c949 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); in cgx_lmac_pause_frm_config()
1017 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg); in cgx_lmac_pfc_config()
1020 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); in cgx_lmac_pfc_config()
1516 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); in cgx_set_link_mode()
1517 req = FIELD_SET(CMDMODECHANGE_SPEED, in cgx_set_link_mode()
1520 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); in cgx_set_link_mode()
1522 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); in cgx_set_link_mode()
1536 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req); in cgx_set_fec()
1537 req = FIELD_SET(CMDSETFEC, fec, req); in cgx_set_fec()
1572 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req); in cgx_fwi_link_change()
[all …]
A Drpm.c397 cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg); in rpm_lmac_pause_frm_config()
473 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req); in rpm_get_lmac_type()
659 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, class_en); in rpm_lmac_pfc_config()
663 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, 0, class_en); in rpm_lmac_pfc_config()
A Dcgx_fw_if.h183 #define FIELD_SET(m, y, x) \ macro
/drivers/gpu/drm/xe/tests/
A Dxe_rtp_test.c229 XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,

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