| /drivers/gpu/drm/armada/ |
| A D | armada_fb.c | 30 #define FMT(drm, fmt, mod) \ in armada_framebuffer_create() macro
35 FMT(RGB565, 565, CFG_SWAPRB); in armada_framebuffer_create()
36 FMT(BGR565, 565, 0); in armada_framebuffer_create()
38 FMT(ABGR1555, 1555, 0); in armada_framebuffer_create()
40 FMT(BGR888, 888PACK, 0); in armada_framebuffer_create()
42 FMT(XBGR8888, X888, 0); in armada_framebuffer_create()
44 FMT(ABGR8888, 8888, 0); in armada_framebuffer_create()
49 FMT(YUV422, 422, CFG_YUV2RGB); in armada_framebuffer_create()
51 FMT(YUV420, 420, CFG_YUV2RGB); in armada_framebuffer_create()
53 FMT(C8, PSEUDO8, 0); in armada_framebuffer_create()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_opp.h | 44 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
46 SRI(FMT_CONTROL, FMT, id), \
47 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
50 SRI(FMT_CLAMP_CNTL, FMT, id), \
51 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
52 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
53 SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
86 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
88 SRI(FMT_CONTROL, FMT, id), \
[all …]
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| /drivers/gpu/drm/amd/display/dc/opp/dcn10/ |
| A D | dcn10_opp.h | 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
38 SRI(FMT_CONTROL, FMT, id), \
39 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
40 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
41 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
42 SRI(FMT_CLAMP_CNTL, FMT, id), \
43 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
44 SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
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| /drivers/media/platform/amlogic/meson-ge2d/ |
| A D | ge2d.c | 100 #define FMT(_fourcc, _alpha, _depth, _map) \ macro
112 FMT(V4L2_PIX_FMT_XRGB32, false, 32, BGRA8888),
113 FMT(V4L2_PIX_FMT_RGB32, true, 32, BGRA8888),
114 FMT(V4L2_PIX_FMT_ARGB32, true, 32, BGRA8888),
116 FMT(V4L2_PIX_FMT_RGBA32, true, 32, ABGR8888),
118 FMT(V4L2_PIX_FMT_BGRA32, true, 32, RGBA8888),
119 FMT(V4L2_PIX_FMT_BGR32, true, 32, ARGB8888),
120 FMT(V4L2_PIX_FMT_ABGR32, true, 32, ARGB8888),
123 FMT(V4L2_PIX_FMT_RGB24, false, 24, BGR888),
124 FMT(V4L2_PIX_FMT_BGR24, false, 24, RGB888),
[all …]
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| /drivers/mmc/core/ |
| A D | sdio_cis.c | 337 #define FMT(type) "%s: queuing " type " CIS tuple 0x%02x [%*ph] (%u bytes)\n" in sdio_read_cis() macro
343 pr_debug_ratelimited(FMT("vendor"), in sdio_read_cis()
348 pr_warn_ratelimited(FMT("unknown"), in sdio_read_cis()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_opp.h | 34 SRI(FMT_422_CONTROL, FMT, id)
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_opp.h | 39 SRI(FMT_422_CONTROL, FMT, id)
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 541 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \
542 SRI_ARR(FMT_DITHER_RAND_R_SEED, FMT, id), \
543 SRI_ARR(FMT_DITHER_RAND_G_SEED, FMT, id), \
544 SRI_ARR(FMT_DITHER_RAND_B_SEED, FMT, id), \
545 SRI_ARR(FMT_CLAMP_CNTL, FMT, id), \
546 SRI_ARR(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
547 SRI_ARR(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
563 SRI_ARR(FMT_422_CONTROL, FMT, id)
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| /drivers/gpu/drm/amd/display/dc/opp/dcn20/ |
| A D | dcn20_opp.h | 49 SRI(FMT_422_CONTROL, FMT, id), \
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| /drivers/s390/cio/ |
| A D | chsc.c | 1030 #define chsc_det_chp_desc(FMT, c) \ argument
1031 int chsc_determine_fmt##FMT##_channel_path_desc( \
1032 struct chp_id chpid, struct channel_path_desc_fmt##FMT *desc) \
1040 ret = chsc_determine_channel_path_desc(chpid, 0, FMT, c, 0, \
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| /drivers/gpu/drm/radeon/ |
| A D | r300_reg.h | 929 # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ argument
934 | (R300_TX_FORMAT_##FMT) \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 53 SRI_ARR(FMT_422_CONTROL, FMT, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 413 SRI_ARR(FMT_422_CONTROL, FMT, id)
|