Searched refs:FW_BLC_SELF (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| A D | cdv_intel_display.c | 472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
476 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
535 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
536 REG_READ(FW_BLC_SELF); in cdv_update_wm()
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| A D | psb_intel_reg.h | 566 #define FW_BLC_SELF 0x20e0 macro
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| /drivers/gpu/drm/i915/display/ |
| A D | i9xx_wm.c | 161 was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
162 intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()
163 intel_de_posting_read(display, FW_BLC_SELF); in _intel_set_memory_cxsr()
174 was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
177 intel_de_write(display, FW_BLC_SELF, val); in _intel_set_memory_cxsr()
178 intel_de_posting_read(display, FW_BLC_SELF); in _intel_set_memory_cxsr()
2335 intel_de_write(display, FW_BLC_SELF, in i9xx_update_wm()
2338 intel_de_write(display, FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
3765 wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
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| A D | intel_display_debugfs.c | 101 sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
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| /drivers/gpu/drm/i915/ |
| A D | i915_reg.h | 414 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ macro
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